################################################################################
# Vivado (TM) v2016.4 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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温馨提示
使用VIVADO进行信号的调制与解调,题目:(1)载波信号频率范围:1M-10MHz,分辨率0.01MHz; (2)调制信号为单频正弦波信号,频率范围:1kHz-10kHz,分辨率0.01kHz; (3)AM波表达式[1+ma(cosW1t+cosW2t)]cosWct (4)调制深度0-1.0,步进0.1,精度优于5%; (5)调制信号位宽为 位和解调信号位宽为 位,其他信号位宽自定义,解调误差优于1%,并利用MATLAB对数据进行验证; (6)载波信号频率、调制信号频率和调制深度由VIO控制,调制、解调等信号利用ILA进行观察,观察数据长度为 ; (7)仿真时设置载波信号频率 MHz,调制信号频率 1+4 kHz,调制深度 ;
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收起资源包目录
使用VIVADO进行FPGA信号的调制与解调 (1338个子文件)
xsim.ini.bak 16KB
elaborate.bat 705B
compile.bat 457B
simulate.bat 265B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
basic.bit 9.28MB
hw_ila_data_1_11156_1558143640.btree 5.25MB
tb_fir_compiler_0.c 8KB
fir-ditong.coe 1000B
fir-ditong.coe 1000B
fir-ditong.coe 1000B
fir-ditong.coe 1000B
fir-ditong.coe 1000B
fir-ditong.coe 1000B
fir-ditong.coe 1000B
fir-ditong.coe 1000B
fir-ditong.coe 1000B
fir-ditong.coe 1000B
iladata.csv 293KB
xsim.dbg 21KB
basic_routed.dcp 6.11MB
basic_placed.dcp 4.93MB
basic_opt.dcp 3.64MB
ila.dcp 2.35MB
ila.dcp 2.35MB
ila.dcp 2.34MB
ila.dcp 1.23MB
fir_compiler_0.dcp 680KB
fir_compiler_0.dcp 460KB
fir_compiler_0.dcp 460KB
fir_compiler_0.dcp 459KB
dbg_hub_CV.dcp 278KB
vio.dcp 186KB
vio.dcp 186KB
vio.dcp 185KB
vio.dcp 182KB
mult2.dcp 51KB
mult_gen_0.dcp 51KB
dds_tiaozhi1K.dcp 49KB
dds_tiaozhi3K.dcp 49KB
dds_tiaozhi3K.dcp 49KB
dds_tiaozhi1K.dcp 49KB
dds_tiaozhi1K.dcp 49KB
dds_tiaozhi1K.dcp 47KB
dds_gaopinzaibo.dcp 43KB
dds_gaopinzaibo.dcp 43KB
dds_gaopinzaibo.dcp 43KB
mult1.dcp 31KB
mult1.dcp 31KB
mult1.dcp 30KB
sub2.dcp 30KB
sub2.dcp 30KB
sub2.dcp 30KB
sub1.dcp 27KB
sub1.dcp 27KB
sub1.dcp 27KB
basic.dcp 25KB
clk.dcp 12KB
clk.dcp 12KB
clk.dcp 12KB
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资源评论
- 吉利吉利2023-07-26这篇文件对于使用VIVADO进行FPGA信号的调制与解调提供了详尽的指导,非常实用。
- 我只匆匆而过2023-07-26这篇文件在FPGA信号调制解调的研究中扮演了重要角色,值得更多人了解和参考。
- 我有多作怪2023-07-26作者用简洁的语言描述了使用VIVADO进行FPGA信号调制解调的过程,大大提高了阅读的效率。
- 王元祺2023-07-26文件中的步骤清晰易懂,让人可以快速上手操作FPGA信号调制解调的技术。
- 永远的122023-07-26阅读这篇文件后,我对FPGA信号调制解调的原理有了更深刻的理解,可以更好地应用到实际项目中。
f1275928612
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