2 EE108 Class Notes
4 CMOS Logic Circuits 47
4.1 SwitchLogic ............................. 47
4.2 ASwitchModelofMOSTransistors ................ 52
4.3 CMOSGateCircuits......................... 57
4.4 BibliographicNotes.......................... 65
4.5 Exercises ............................... 66
5 Delay and Power of CMOS Circuits 67
5.1 DelayofStaticCMOSGates .................... 67
5.2 Fanout and Driving Large Loads . . . . . . . . . . . . . . . . . . 70
5.3 Fan-inandLogicalEffort ...................... 72
5.4 DelayCalculation........................... 73
5.5 OptimizingDelay........................... 77
5.6 WireDelay .............................. 78
5.7 PowerDissipationinCMOSCircuits................ 79
5.8 BibliographicNotes.......................... 81
5.9 Exercises ............................... 81
6 Combinational Logic Design 83
6.1 CombinationalLogic......................... 83
6.2 Closure ................................ 84
6.3 TruthTables,Minterms,andNormalForm ............ 85
6.4 ImplicantsandCubes ........................ 88
6.5 KarnaughMaps............................ 91
6.6 CoveringaFunction ......................... 92
6.7 FromaCovertoGates........................ 95
6.8 Incompletely Specified Functions (Dont’ Cares) . . . . . . . . . . 95
6.9 Product-of-Sums Implementation . . . . . . . . . . . . . . . . . . 97
6.10Hazards ................................ 99
6.11Summary ...............................101
6.12BibliographicNotes..........................102
6.13Exercises ...............................102
7 Verilog Descriptions of Combinational Logic 107
7.1 The Prime Number Circuit in Verilog . . . . . . . . . . . . . . . 107
7.1.1 AVerilogModule.......................108
7.1.2 TheCaseStatement .....................109
7.1.3 TheCaseXStatement ....................111
7.1.4 TheAssignStatement....................112
7.1.5 StructuralDescription....................113
7.1.6 The Decimal Prime Number Function . . . . . . . . . . . 115
7.2 ATestbenchforthePrimeCircuit .................115
7.3 Example, A Seven-Segment Decoder . . . . . . . . . . . . . . . . 119
7.4 BibliographicNotes..........................125
7.5 Exercises ...............................125
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