JEDEC Standard No. 82-521
CONTENTS
DDR5 Data Buffer Definition (DDR5DB01)...............................................................................................................1
1 Scope
...........................................................................................................................................................................1
2 Mechanical Outline ...................................................................................................................................................1
2.1 Pinout 15 x 5 ............................................................................................................................................................2
2.2 Terminal Functions for 55-Ball Data Buffer Package Configuration
......................................................................2
3 Device Description and Features
.............................................................................................................................3
3.1 Description ...............................................................................................................................................................3
3.2 Power-on Initialization.............................................................................................................................................3
3.2.1 Clock Stabilization Time tSTAB_DB
...................................................................................................................4
3.2.2 Reset Initialization with Stable Power ..................................................................................................................4
3.3 Transparent Mode ....................................................................................................................................................5
3.4 DQ Pass-Through Mode
..........................................................................................................................................6
3.5 Loopback Mode
.......................................................................................................................................................7
3.5.1 Loopback Output Definition .................................................................................................................................7
3.5.2 Loopback Phase ....................................................................................................................................................8
3.5.3 Loopback Output Mode
........................................................................................................................................9
3.5.3.1 Loopback DQS Qualified Output Mode (Default) ..........................................................................................10
3.5.3.2 Loopback DQS Qualified Output Mode Timing Diagrams.............................................................................10
3.5.3.3 Loopback WE Qualified Output Mode
............................................................................................................10
3.5.3.4 Loopback WE Qualified Output Mode Timing Diagrams
...............................................................................11
3.5.4 Loopback Timing and Levels .............................................................................................................................15
3.6 ZQ Calibration .......................................................................................................................................................16
3.7 Continuous Burst Mode
.........................................................................................................................................16
3.8 Dynamic ODT Control on the Host interface ........................................................................................................17
3.8.1 ODT Functional Description...............................................................................................................................39
3.8.2 ODT tADC Clarifications
...................................................................................................................................41
3.8.3 ODT Timing Diagrams
.......................................................................................................................................41
3.9 DRAM Periodic Update Support ...........................................................................................................................21
3.9.1 DRAM tDQS2DQ Tracking Modes
...................................................................................................................44
3.9.2 Operational Requirements..................................................................................................................................44
3.9.3 DRAM tDQS2DQ Tracking Initialization Mode
................................................................................................45
3.9.4 DRAM tDQS2DQ Tracking Mode .....................................................................................................................46
3.9.5 MDQ-MDQS Adjustment Calculations..............................................................................................................47
3.9.6 DRAM interval Oscillator Snoop Value
.............................................................................................................48
4 Power Down operation ...........................................................................................................................................27
4.1 Power Savings Modes............................................................................................................................................27
4.1.1 PDE Power Down Mode
.....................................................................................................................................50
4.1.2 PDE Power Down Mode with ODT Control Enabled
........................................................................................50
4.1.3 PDE Power Down Mode without ODT Control Disabled ..................................................................................51
4.2 Self Refresh Modes
................................................................................................................................................28
4.2.1 Self Refresh Mode with Clock Stop Entry..........................................................................................................51
4.2.2 Exit from Self Refresh Mode with Clock Stop ...................................................................................................52
4.2.3 Self Refresh Mode without Clock Stop Entry
....................................................................................................52
4.2.4 Self Refresh Mode without Clock Stop Exit
.......................................................................................................52
5 Data Buffer Control Bus.........................................................................................................................................33
5.1 Control Bus Signals ...............................................................................................................................................33
5.1.1 Control Bus Signal Termination .........................................................................................................................56
5.1.2 Control Bus Timing
............................................................................................................................................56
5.2 Control Bus Commands .........................................................................................................................................36
5.2.1 Data Buffer Control Bus Command Truth Table
................................................................................................59
5.3 Command Sequences
.............................................................................................................................................36
5.3.1 Command Sequence Descriptions ......................................................................................................................36
5.3.2 WR/RD Burst Length Processing .......................................................................................................................38
5.3.3 Control Word Burst Length Processing
..............................................................................................................39
5.3.4 MRW Commands ...............................................................................................................................................40
5.3.5 MRR Commands
.................................................................................................................................................41
5.3.5.1 Multi-cycle Sequence for MRR Commands....................................................................................................41
5.3.5.2 Short MRR Command for SDR Training.
.......................................................................................................42
5.3.6 WR Commands ...................................................................................................................................................47
5.3.7 RD Commands....................................................................................................................................................48
5.3.8 PDE Commands..................................................................................................................................................50
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