Abstract
New applications such as artificial intelligence, autonomous cars, high performance
computing, and embedded vision are driving stricter requirements for memory
performance and power efficiency. These demands led the new mobile DRAM
technology evolved to the fifth generation (LPDDR5). LPDDR5 delivers significant
reduction in power and extremely high bandwidth as compared to LPDDR4. In this
paper, we present various bandwidth improvement techniques which enable world’s first
6.4 Gbps/pin LPDDR5 interface. The achieved READ and WRITE valid window
margin(VWM) at 6.4 Gbps are 0.36 UI and 0.4 UI, respectively. The measured WCK
clock duty was within 43~57% at 3.2 GHz including process variation and peak-to-peak
periodic jitter was less than 20ps. Also various measured results will be shown as
enabling references for other LPDDR5 interface designers.
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Author’s Biographies
Billy(Kyounghoi) Koo received B.S. and M.S. degrees in electrical engineering from
Chungbuk National University, Korea in 1996 and 1998, respectively with focus on high
speed I/O transceiver. In 1998, he joined SAMSUNG Electronics where he was designed
and developed high-speed peripheral interfaces such as PCI-X, AGP, HSTL, SSTL,
LVDS and USB2.0. From 2004 to current, he was responsible for the developing high-
speed memory interface circuits for native DDR2/DDR3/DDR4 and mobile
LPDDR2/LPDDR3/LPDDR4. He holds over 10 U.S. and foreign patents, and published
6 papers and conference contributions in analog/digital mixed signal design and high-
speed interface area.
Jinho choi received the B.S. and M.S. degrees in electronics engineering from Chung-
Ang University, Seoul, Korea, in 2003 and 2005. Jinho Choi is a senior engineer in
Samsung Electronics, where he is working the various memory interface circuit design in
the specialization of high-speed I/O interface, low-power CMOS circuit design and
analog circuit design.
Kwanyeob Chae received the B.S. and M.S. degrees in electronics engineering from
Korea University, Seoul, Korea, in 1998 and 2000, respectively, and the Ph.D. degree in
electrical and computer engineering from Georgia Institute of Technology, Atlanta in
2013. Kwanyeob Chae is a principal engineer in Samsung Electronics, where he is
leading the architecture and implementation part. His research interests include high-
speed/low-power digital interface circuits, self-adaptive circuits and systems, variation-
tolerant design, and 3-D ICs.
