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library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.std_logic_unsigned.ALL;
use ieee.std_logic_arith.all;
-- -----------------------------------------------
Entity amdds_module is
-- -----------------------------------------------
Port 
( 
 CLK   : in  std_logic;
 Freq_Data_1 : in  std_logic_vector (31 downto 0);
 Freq_Data_2 : in  std_logic_vector (31 downto 0);
 Dout   : out std_logic_vector (7 downto 0) 
);
end amdds_module;
-- -----------------------------------------------
Architecture RTL of amdds_module is
-- -----------------------------------------------
signal Address_1  : std_logic_vector(7 downto 0);
signal Address_2  : std_logic_vector(7 downto 0);
signal Accum_1   : std_logic_vector (31 downto 0);
signal Accum_2   : std_logic_vector (31 downto 0);  
begin
--------------------------------------------------
Acc_1: process (CLK)
begin
if rising_edge(CLK) then
Accum_1 <= Accum_1 +Freq_Data_1+Freq_Data_2;
end if;