UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 1.6 — 25 January 2013 3 of 1316
NXP Semiconductors
UM10503
LPC43xx user manual
Modifications: • ETM time stamping feature not implemented. See Chapter 49.
• Bit 0 in the RGU RESET_STATUS0 register changed to reserved. Section 13.5.1 “Determine the
cause of a core reset” added.
• Micron part N25Q256 removed from the list of devices supported by the SPIFI boot ROM driver and
API. (See Table 387 “QSPI devices not supported by the boot code”.) Section 22.6 updated.
• Part S25FL129P0XNFI01 added to the list of devices supported by the SPIFI boot ROM driver.
• SGPIO register descriptions for CTRL_ENABLED and CTRL_DISABLED registers updated (see
Table 230 and Table 231).
• Section 21.7.5 “Dynamic Memory Refresh Timer register” register description updated.
• Description of the Motor control PWM INVDC bit updated in Table 734 “MCPWM Control read
address (CON - 0x400A 0000) bit description”.
• Description of the Alarm timer PRESETVAL bit updated in Table 799 “Preset value register (PRESET
- 0x4004 0004) bit description”.
• Description of ADC pins on digital/analog input pins changed. Each input to the ADC is connected to
ADC0 and ADC1. See Table 128, Table 129, Table 1040, and Section 15.1.
• Description of extra status bits added to Table 568 “DMA Status register (DMA_STAT, address
0x4001 1014) bit description”.
• Use of lower SPIFI memory clarified in Table 384 “SPIFI flash memory map”.
• Description of DAC DMA_ENA bit clarified in Table 1054 “D/A Control register (CTRL - address
0x400E 1004) bit description”.
• Pseudo-code for PLL registers updated by code snippets from LPC43xx sample code in Chapter 11.
• Reset delay clock cycles explained in Section 13.4.1 “RGU reset control register”.
1.4 20120903 LPC43xx user manual.
Modifications: • SSP0 boot pin functions corrected in Table 18 and Table 19. Pin P3_3 = SSP0_SCK, pin P3_6 =
SSP0_SSEL, pin P3_7 = SSP0_MISO, pin P3_8 = SSP0_MOSI.
• CLKMODE3 removed from the SCT. Bit value CLKMODE = 0x3 changed to reserved in Table 647
“SCT configuration register (CONFIG - address 0x4000 0000) bit description”.
• SWD mode removed for ARM Cortex-M0.
• Details for GIMA clock synchronization added in Section 16.3.2.
• RESET_EXT_STATUS0 register removed in Chapter 13.
• Reset value of BASE_SAFE_CLK register changed to R (read-only) in Table 84.
• Reset delay values corrected in Figure 31 “RGU Reset structure”.
• RGU reset values corrected in Table 113 “Register overview: RGU (base address: 0x4005 3000)”.
• Editorial updates in Chapter 18 “LPC43xx Serial GPIO (SGPIO)”.
• POR reset value of the event router STATUS register corrected in Table 31 and Table 37.
• USB boot mode updated: 12 MHz external crystal required. See Section 5.3.5.5.
• IAP invoke call entry pointer clarified in Section 46.8.
• EMC memory data and control lines clarified for the LQFP208 package in Table 349.
• Figure 11 updated to include boot process for AES capable parts.
• Editorial updates.
Revision history
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Rev Date Description
