Section number Title Page
5.1 Introduction...................................................................................................................................................................91
5.2 Device security..............................................................................................................................................................91
5.2.1 Flash memory security...................................................................................................................................91
5.2.2 Cryptographic Services Engine (CSEc) security features..............................................................................92
5.2.3 Device Boot modes........................................................................................................................................ 93
5.3 Security use case examples...........................................................................................................................................93
5.3.1 Secure boot: check bootloader for integrity and authenticity........................................................................ 93
5.3.2 Chain of trust: check flash memory for integrity and authenticity................................................................ 94
5.3.3 Secure communication...................................................................................................................................95
5.3.4 Component protection....................................................................................................................................96
5.3.5 Message-authentication example................................................................................................................... 97
5.4 Steps required before failure analysis...........................................................................................................................98
5.5 Security programming flow example (Secure Boot).................................................................................................... 99
Chapter 6
Safety Overview
6.1 Introduction...................................................................................................................................................................101
6.2 S32K1xx safety concept............................................................................................................................................... 102
6.2.1 Cortex-M4/M0+ Structural Core Self Test (SCST).......................................................................................103
6.2.2 ECC on RAM and flash memory...................................................................................................................104
6.2.3 Power supply monitoring...............................................................................................................................104
6.2.4 Clock monitoring........................................................................................................................................... 105
6.2.5 Temporal protection.......................................................................................................................................105
6.2.6 Operational interference protection............................................................................................................... 105
6.2.7 CRC................................................................................................................................................................107
6.2.8 Diversity of system resources........................................................................................................................ 107
Chapter 7
CM4 Overview
7.1 Arm Cortex-M4F core configuration............................................................................................................................109
7.1.1 Buses, interconnects, and interfaces.............................................................................................................. 110
S32K1xx Series Reference Manual, Rev. 9, 09/2018
NXP Semiconductors 5
