at91sam9260 nandflash说明文档

NAND Flash Support in AT91SAM9

Microcontrollers

1. Scope

The purpose of this application note is to introduce the NAND Flash technology and to

describe how to interface NAND Flash memory to Atmel

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AT91SAM9 ARM

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Thumb

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based Microcontrollers that do not feature a NAND Flash Controller. The NAND Flash

logic is driven by the Static Memory Controller on the NCS3 address space.

optimal for storage applications

The NAND Flash used to illustrate this interface is the K9F2G08U0M, manufactured

by Samsung

bit. The cell area of NAND Flash is smaller than that of NOR Flash, making the NAND Flash

more cost effective than NOR Flash.

The first significant difference between NAND and NOR Flash is the hardware interface.

2.2.1 Hardware Interface

NOR Flash has a fully memory-mapped random access interface similar to a RAM, with dedi-

cated address lines and data lines making it “bootable”.

NAND Flash uses a multiplexed I/O interface and additional control signals. It is controlled by

– I/O[7:0] or I/O[15:0] - data bus

NAND Flash is also divided into blocks which contain many pages instead of words (2K +64

After this selection, the entire page can be read or written.

NAND provides over five megabytes per second of sustained write performance. The block

erase times are an impressive 2 ms for NAND versus 200 ms for NOR.

2.2.4 Conclusion

Table 2-2 summarizes NAND/NOR advantages and disadvantages.

Characteristics

K9F2G08U0M

NOR Flash

Random write speed 300 µs/2,112 bytes 20 µs / bytes

basis)

5 Mbytes/s 0.05 Mbytes/s

Erase block size 128 Kbytes 64 Kbytes

NAND NOR

Advantages

Any large sequential data

NAND is available in large capacities and is the lowest cost Flash memory available today.

NAND is used in virtually all removable cards for cost/density reasons: USB Cards, Memory

Stick, MMC Multimedia Card, SD Secure Digital, CF Compact Flash.

invalid memory blocks. If the application code executes from RAM rather than Flash memory,

updates.

All device locations are erased (FFh for X8, FFFFh for X16) except locations where the invalid

block information is written prior to shipping. The invalid block status is defined by the 1st byte

The 1st or 2nd page of every invalid block has non-FFh(X8) or non-FFFFh(X16) data at the col-

umn address of 2048 (X8 device) or 1024 (X16 device). Since the invalid block information is