PCI EXPRESS BASE SPECIFICATION, REV. 2.0
4
2.3.2. Completion Handling Rules.................................................................................. 98
2.4. TRANSACTION ORDERING............................................................................................ 100
2.4.1. Transaction Ordering Rules ............................................................................... 100
2.4.2. Update Ordering and Granularity Observed by a Read Transaction................ 104
2.4.3. Update Ordering and Granularity Provided by a Write Transaction................ 105
2.5. VIRTUAL CHANNEL (VC) MECHANISM........................................................................ 105
2.5.1. Virtual Channel Identification (VC ID).............................................................. 108
2.5.2. TC to VC Mapping.............................................................................................. 109
2.5.3. VC and TC Rules................................................................................................. 110
2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 111
2.6.1. Flow Control Rules............................................................................................. 112
2.7. DATA INTEGRITY ......................................................................................................... 122
2.7.1. ECRC Rules ........................................................................................................ 123
2.7.2. Error Forwarding............................................................................................... 127
2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 129
2.9. LINK STATUS DEPENDENCIES ...................................................................................... 130
2.9.1. Transaction Layer Behavior in DL_Down Status............................................... 130
2.9.2. Transaction Layer Behavior in DL_Up Status ................................................... 131
3. DATA LINK LAYER SPECIFICATION.......................................................................... 133
3.1. DATA LINK LAYER OVERVIEW .................................................................................... 133
3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 135
3.2.1. Data Link Control and Management State Machine Rules ................................ 136
3.3. FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 138
3.3.1. Flow Control Initialization State Machine Rules ............................................... 138
3.4. DATA LINK LAYER PACKETS (DLLPS)........................................................................ 142
3.4.1. Data Link Layer Packet Rules ............................................................................ 142
3.5. DATA INTEGRITY ......................................................................................................... 147
3.5.1. Introduction......................................................................................................... 147
3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 147
3.5.3. LCRC and Sequence Number (TLP Receiver).................................................... 159
4. PHYSICAL LAYER SPECIFICATION............................................................................ 167
4.1. INTRODUCTION ............................................................................................................ 167
4.2. L
OGICAL SUB-BLOCK................................................................................................... 167
4.2.1. Symbol Encoding ................................................................................................ 168
4.2.2. Framing and Application of Symbols to Lanes................................................... 171
4.2.3. Data Scrambling................................................................................................. 174
4.2.4. Link Initialization and Training.......................................................................... 176
4.2.5. Link Training and Status State Machine (LTSSM) Descriptions........................ 188
4.2.6. Link Training and Status State Rules.................................................................. 192
4.2.7. Clock Tolerance Compensation.......................................................................... 237
4.2.8. Compliance Pattern ............................................................................................ 239
4.2.9. Modified Compliance Pattern............................................................................. 240
4.3. E
LECTRICAL SUB-BLOCK ............................................................................................. 241
4.3.1. Maintaining Backwards Compatibility............................................................... 241
4.3.2. Jitter Budgeting and Measurement..................................................................... 243
「已注销」2018-10-11这种资源你还要币？你有脸吗？良心不痛吗？原版的官方文档，你居然有脸作为自己的私有文档？当然是共享了！！！你以为你自己写的吗？
taipeirayon2011-10-252.0是否可以比1.1快到底如何達成.這資料可以看其相容性.
piaohuaxuanfeng2013-06-132.0和3.0 spec内容区别不是很大,看过其中一个,另外一份就容易看懂了.
