HIGH SPEED SERIALIZED AT ATTACHMENT
Serial ATA International Organization
Serial ATA Revision 3.0 - Gold Revision
Serial ATA International Organization:
Serial ATA Revision 3.0
27-May-2009
Gold Revision
SATA-IO Board Members:
Dell Computer Corporation
Hewlett Packard Corporation
Hitachi Global Storage Technologies, Inc.
Intel Corporation
Maxim Integrated Products
Seagate Technology
Western Digital Corporation
Serial ATA Revision 3.0 Gold Revision page 2 of 663
Serial ATA International Organization: Serial ATA Revision 3.0 specification ("Final Specification")
is available for download at www.sata-io.org.
SPECIFICATION DISCLAIMER
THIS SPECIFICATION IS PROVIDED TO YOU “AS IS” WITH NO WARRANTIES
WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-
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SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF
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YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS.
Copyright 2002-2009, Serial ATA International Organization. All rights reserved.
For more information about Serial ATA, refer to the Serial ATA International Organization website
at www.sata-io.org
.
All product names are trademarks, registered trademarks, or servicemarks of their respective
owners.
Serial ATA International Organization contact information:
SATA-IO
3855 SW 153
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Drive
Beaverton, Oregon 97006 USA
Tel: +1 503-619-0572
Fax: +1 503-644-6708
E-mail: admin@sata-io.org
Serial ATA Revision 3.0 Gold Revision page 3 of 663
TABLE OF CONTENTS
1 Revision History....................................................................................................................23
1
.1
R
evision 2.5 (Ratification Date October 27, 2005) ........................................................ 23
1.2 Revision 2.6 (Ratification Date February 15, 2007) ...................................................... 23
1.3 Revision 3.0 (Release Candidate 2: May 15, 2009)..................................................... 23
2 Scope....................................................................................................................................25
3 Normative references ...........................................................................................................27
3.1 Approved references ..................................................................................................... 27
3.2 References under development .................................................................................... 29
3.3 Other references............................................................................................................ 29
4 Definitions, abbreviations, and conventions .........................................................................31
4.1 Definitions and abbreviations ........................................................................................ 31
4.1.1 Active Port ............................................................................................................. 31
4.1.2 ATA (AT Attachment)............................................................................................. 31
4.1.3 ATAPI (AT Attachment Packet Interface) device .................................................. 31
4.1.4 BER (bit error rate) ................................................................................................ 31
4.1.5 bitrate ..................................................................................................................... 31
4.1.6 bit synchronization ................................................................................................. 31
4.1.7 burst ....................................................................................................................... 31
4.1.8 byte ........................................................................................................................ 31
4.1.9 character................................................................................................................ 31
4.1.10 character alignment ............................................................................................... 31
4.1.11 character slipping................................................................................................... 31
4.1.12 ClickConnect.......................................................................................................... 32
4.1.13 CLTF (Closed Loop Transfer Function)................................................................. 32
4.1.14 code violation......................................................................................................... 32
4.1.15 comma character ................................................................................................... 32
4.1.16 comma sequence .................................................................................................. 32
4.1.17 command aborted.................................................................................................. 32
4.1.18 command completion............................................................................................. 32
4.1.19 command packet ................................................................................................... 32
4.1.20 concentrator........................................................................................................... 33
4.1.21 Control Block registers........................................................................................... 33
4.1.22 control character .................................................................................................... 33
4.1.23 control port............................................................................................................. 33
4.1.24 control variable ...................................................................................................... 33
4.1.25 CRC (Cyclic Redundancy Check) ......................................................................... 33
4.1.26 data character........................................................................................................ 33
4.1.27 data signal source.................................................................................................. 33
4.1.28 device..................................................................................................................... 33
4.1.29 device port ............................................................................................................. 33
4.1.30 DCB (DC block) ..................................................................................................... 33
4.1.31 differential signal.................................................................................................... 34
4.1.32 DJ (deterministic jitter – peak to peak) .................................................................. 34
4.1.33 DMA (direct memory access) ................................................................................ 34
4.1.34 Dword..................................................................................................................... 34
4.1.35 Dword synchronization .......................................................................................... 34
4.1.36 EMI (Electromagnetic Interference)....................................................................... 34
4.1.37 encoded character ................................................................................................. 34
4.1.38 endpoint device...................................................................................................... 34
4.1.39 elasticity buffer....................................................................................................... 34
4.1.40 eSATA.................................................................................................................... 34
4.1.41 Fbaud..................................................................................................................... 35
4.1.42 FER (frame error rate) ........................................................................................... 35
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4.1.43
First-party DMA Data Phase.................................................................................. 35
4.1.44 First-party DMA access ......................................................................................... 35
4.1.45 FIS (Frame Information Structure)......................................................................... 35
4.1.46 frame...................................................................................................................... 35
4.1.47 Gen1 ...................................................................................................................... 35
4.1.48 Gen1i ..................................................................................................................... 35
4.1.49 Gen1m ................................................................................................................... 35
4.1.50 Gen1x .................................................................................................................... 35
4.1.51 Gen2 ...................................................................................................................... 35
4.1.52 Gen2i ..................................................................................................................... 35
4.1.53 Gen2m ................................................................................................................... 35
4.1.54 Gen2x .................................................................................................................... 36
4.1.55 Gen3 ...................................................................................................................... 36
4.1.56 Gen3i ..................................................................................................................... 36
4.1.57 HBA (Host Bus Adapter)........................................................................................ 36
4.1.58 HBWS (High Bandwidth Scope) ............................................................................ 36
4.1.59 HFTP (High Frequency Test Pattern).................................................................... 36
4.1.60 hot plug .................................................................................................................. 36
4.1.61 host port ................................................................................................................. 36
4.1.62 inactive port ........................................................................................................... 36
4.1.63 interrupt pending.................................................................................................... 36
4.1.64 immediate NCQ command .................................................................................... 37
4.1.65 ISI (inter-symbol interference) ............................................................................... 37
4.1.66 JMD (jitter measuring device)................................................................................ 37
4.1.67 JTF (Jitter Transfer Function) ................................................................................ 37
4.1.68 junk ........................................................................................................................ 37
4.1.69 LBA (Logical Block Address) ................................................................................. 37
4.1.70 LBP (Lone Bit Pattern)........................................................................................... 37
4.1.71 LED (Light Emitting Diode) .................................................................................... 37
4.1.72 legacy mode .......................................................................................................... 38
4.1.73 legal character ....................................................................................................... 38
4.1.74 LFSR (Linear Feedback Shift Register)................................................................. 38
4.1.75 LFTP (low frequency test pattern) ......................................................................... 38
4.1.76 LL (laboratory load)................................................................................................ 38
4.1.77 LSS (laboratory sourced signal or lab-sourced signal).......................................... 38
4.1.78 MFTP (mid frequency test pattern)........................................................................ 38
4.1.79 NCQ streaming command ..................................................................................... 38
4.1.80 NCQ Non-streaming command ............................................................................. 38
4.1.81 OOB (Out-of-Band signaling) ................................................................................ 38
4.1.82 OS-aware hot plug................................................................................................. 39
4.1.83 OS-aware hot removal........................................................................................... 39
4.1.84 Phy offline .............................................................................................................. 39
4.1.85 PIO (programmed input/output)............................................................................. 39
4.1.86 port address ........................................................................................................... 39
4.1.87 PRD (Physical Region Descriptor) ........................................................................ 39
4.1.88 primitive.................................................................................................................. 39
4.1.89 protocol-based port selection ................................................................................ 39
4.1.90 quiescent power condition ..................................................................................... 39
4.1.91 RJ (random jitter) ................................................................................................... 39
4.1.92 sector ..................................................................................................................... 39
4.1.93 SEMB (Serial ATA Enclosure Management Bridge) ............................................. 40
4.1.94 SEP (Storage Enclosure Processor) ..................................................................... 40
4.1.95 Shadow Register Block registers........................................................................... 40
4.1.96 side-band port selection......................................................................................... 40
4.1.97 SMART .................................................................................................................. 40
4.1.98 SSC (spread spectrum clocking) ........................................................................... 40
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4.1.99
surprise hot plug .................................................................................................... 40
4.1.100 surprise hot removal .............................................................................................. 40
4.1.101 SYNC Escape........................................................................................................ 40
4.1.102 TDR (time domain reflectometer) .......................................................................... 40
4.1.103 TIA (timing interval analyzer) ................................................................................. 41
4.1.104 TJ (total jitter) ......................................................................................................... 41
4.1.105 UI (unit interval) ..................................................................................................... 41
4.1.106 unrecoverable error ............................................................................................... 41
4.1.107 UUT (unit under test) ............................................................................................. 41
4.1.108 VNA (vector network analyzer).............................................................................. 41
4.1.109 warm plug .............................................................................................................. 41
4.1.110 word ....................................................................................................................... 41
4.1.111 xSATA.................................................................................................................... 41
4.1.112 zero crossing ......................................................................................................... 41
4.2 Conventions................................................................................................................... 41
4.2.1 Precedence............................................................................................................ 42
4.2.2 Keywords ............................................................................................................... 42
4.2.3 Numbering ............................................................................................................. 43
4.2.4 Dimensions ............................................................................................................ 43
4.2.5 Signal conventions................................................................................................. 43
4.2.6 State machine conventions ................................................................................... 44
4.2.7 Byte, word and Dword Relationships..................................................................... 44
5 General overview..................................................................................................................47
5.1 Architecture.................................................................................................................... 48
5.2 Usage Models................................................................................................................ 49
5.2.1 Internal 1 meter Cabled Host to Device................................................................. 52
5.2.2 Short Backplane to Device .................................................................................... 53
5.2.3 Long Backplane to Device..................................................................................... 54
5.2.4 Internal 4-lane Cabled Disk Arrays........................................................................ 55
5.2.5 System-to-System Interconnects – Data Center Applications (xSATA)................ 57
5.2.6 System-to-System Interconnects – External Desktop Applications (eSATA)........ 59
5.2.7 Proprietary Serial ATA Disk Arrays ....................................................................... 60
5.2.8 Serial ATA and SAS .............................................................................................. 60
5.2.9 Potential External SATA Incompatibility Issues..................................................... 61
5.2.10 Mobile Applications................................................................................................ 61
5.2.11 Port Multiplier Example Applications ..................................................................... 62
6 Cables and Connectors ........................................................................................................67
6.1 Internal cables and connectors...................................................................................... 67
6.1.1 Internal Single Lane Description............................................................................ 67
6.1.2 Connector locations ............................................................................................... 70
6.1.3 Mating interfaces ................................................................................................... 79
6.1.4 Signal cable receptacle connector......................................................................... 83
6.1.5 Signal host plug connector .................................................................................... 85
6.1.6 Backplane connector ............................................................................................. 88
6.1.7 Power cable receptacle connector ........................................................................ 91
6.1.8 Internal single lane cable....................................................................................... 93
6.1.9 Connector labeling................................................................................................. 94
6.1.10 Connector and cable assembly requirements and test procedures ...................... 94
6.1.11 Internal Multilane cables........................................................................................ 98
6.1.12 Mini SATA Internal Multilane ............................................................................... 104
6.2 Internal Micro SATA Connector for 1.8” HDD ............................................................. 111
6.2.1 Usage model........................................................................................................ 111
6.2.2 General description.............................................................................................. 111
6.2.3 Connector location............................................................................................... 111
6.2.4 Mating interfaces ................................................................................................. 114
6.3 Internal Slimline cables and connectors ...................................................................... 120
