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DDR4 最新技术以及测试方法

DesignCon 2013

Agilent Education Forum

Agilent Technologies Education Forum:

Making the Most of DDR4

Agenda

• DDR4 Technology Overview

• DDR4 Controller Phy and System Interconnect

Validation and Compliance Test

• DDR4 Protocol Validation, BIOS and System

Integration and Performance Optimization

• Design and Verification of DDR4 Physical Layer

• Wrap-up and Q&A Time

Making the most of DDR4

January 30, 2013

What is DDR4?

• Not just a DDR3 speed bump

• What you would expect:

– Double the I/O rate to 3.2Gb/s

– Reduced Vdd

– Larger address space

– More sophisticated training

• What you might not have anticipated:

• Significant RAS and Mfg testability improvements

• Rethinking of approach to AC Parametrics specification

• Extensive protocol and signaling changes

• Bank groups and “3DS” support from the start

Making the most of DDR4

January 30, 2013

0.01

0.1

100

1000

10000

8 16 32 64 128 256 512 1024 2048 4096 8192

128

256

512

1TB

Gbits/sec

per Pin

DDR4 Pressed Hard Against the “Memory Wall”

# I/O Pins

Channel

Throughput

(GBytes/sec)

Wide-IO

Serial

Current

Technology

Memory Wall

‘15

‘10

‘12

‘06

‘04

‘02

Materials and

Process Physics

Signal

Propagation

Physics

Making the most of DDR4

January 30, 2013

Revolutionary Technologies Adopted in DDR4

“Memory Wall”

Power x Cost Budget

Speed x Interconnect Complexity

Graphics

Computing

Embedded /

Mobile / Flash

Convergence?

Signaling

Revolution

• Signaling revolution

• Continuous forwarded clock

• Extensive training on all signals

• Controller based timing at DRAM

• CRC with cancel on fail and retry

• Move to serial/embedded clock

• Interconnect revolution

• Direct die stacking

• ~1000 signals die-die

• Silicon Thru Vias

• Computing revolution

• 1e2 to 1e7 processors

• Mobile = desktop

• Direct memory connect

• I/O redefined?

• “Functional” OS and Programming

Making the most of DDR4

January 30, 2013

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