FreeRTOS和FreeMODBUS移植到STM32F103傻瓜教程（Keil5）源程序.zip

/****************************************************************************** * * Copyright (C) 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * Use of the Software is limited solely to applications: * (a) running on a Xilinx device, or * (b) that interact with a Xilinx device through a bus or interconnect. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Except as contained in this notice, the name of the Xilinx shall not be used * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * ******************************************************************************/ /****************************************************************************/ /** * * @file psu_init.c * * This file is automatically generated * *****************************************************************************/ #include <xil_io.h> #include <sleep.h> #include "psu_init.h" #define DPLL_CFG_LOCK_DLY 63 #define DPLL_CFG_LOCK_CNT 625 #define DPLL_CFG_LFHF 3 #define DPLL_CFG_CP 3 #define DPLL_CFG_RES 2 static int mask_pollOnValue(u32 add, u32 mask, u32 value); static int mask_poll(u32 add, u32 mask); static void mask_delay(u32 delay); static u32 mask_read(u32 add, u32 mask); static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt, int d_lfhf, int d_cp, int d_res); static void PSU_Mask_Write(unsigned long offset, unsigned long mask, unsigned long val) { unsigned long RegVal = 0x0; RegVal = Xil_In32(offset); RegVal &= ~(mask); RegVal |= (val & mask); Xil_Out32(offset, RegVal); } void prog_reg(unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) { int rdata = 0; rdata = Xil_In32(addr); rdata = rdata & (~mask); rdata = rdata | (value << shift); Xil_Out32(addr, rdata); } unsigned long psu_pll_init_data(void) { /* * RPLL INIT */ /* * Register : RPLL_CFG @ 0XFF5E0034 * PLL loop filter resistor control * PSU_CRL_APB_RPLL_CFG_RES 0xc * PLL charge pump control * PSU_CRL_APB_RPLL_CFG_CP 0x3 * PLL loop filter high frequency capacitor control * PSU_CRL_APB_RPLL_CFG_LFHF 0x3 * Lock circuit counter setting * PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x339 * Lock circuit configuration settings for lock windowsize * PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f * Helper data. Values are to be looked up in a table from Data Sheet * (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E672C6CU) */ PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E672C6CU); /*##################################################################### */ /* * UPDATE FB_DIV */ /* * Register : RPLL_CTRL @ 0XFF5E0030 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source * PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 * The integer portion of the feedback divider to the PLL * PSU_CRL_APB_RPLL_CTRL_FBDIV 0x2d * This turns on the divide by 2 that is inside of the PLL. This does not c * hange the VCO frequency, just the output frequency * PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 * PLL Basic Control * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00012D00U) */ PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00012D00U); /*##################################################################### */ /* * BY PASS PLL */ /* * Register : RPLL_CTRL @ 0XFF5E0030 * Bypasses the PLL clock. The usable clock will be determined from the POS * T_SRC field. (This signal may only be toggled after 4 cycles of the old * clock and 4 cycles of the new clock. This is not usually an issue, but d * esigners must be aware.) * PSU_CRL_APB_RPLL_CTRL_BYPASS 1 * PLL Basic Control * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) */ PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); /*##################################################################### */ /* * ASSERT RESET */ /* * Register : RPLL_CTRL @ 0XFF5E0030 * Asserts Reset to the PLL. When asserting reset, the PLL must already be * in BYPASS. * PSU_CRL_APB_RPLL_CTRL_RESET 1 * PLL Basic Control * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) */ PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); /*##################################################################### */ /* * DEASSERT RESET */ /* * Register : RPLL_CTRL @ 0XFF5E0030 * Asserts Reset to the PLL. When asserting reset, the PLL must already be * in BYPASS. * PSU_CRL_APB_RPLL_CTRL_RESET 0 * PLL Basic Control * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) */ PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); /*##################################################################### */ /* * CHECK PLL STATUS */ /* * Register : PLL_STATUS @ 0XFF5E0040 * RPLL is locked * PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1 * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U) */ mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000002U); /*##################################################################### */ /* * REMOVE PLL BY PASS */ /* * Register : RPLL_CTRL @ 0XFF5E0030 * Bypasses the PLL clock. The usable clock will be determined from the POS * T_SRC field. (This signal may only be toggled after 4 cycles of the old * clock and 4 cycles of the new clock. This is not usually an issue, but d * esigners must be aware.) * PSU_CRL_APB_RPLL_CTRL_BYPASS 0 * PLL Basic Control * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) */ PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); /*##################################################################### */ /* * Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048 * Divisor value for this clock. * PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2 * Control for a clock that will be generated in the LPD, but used in the F * PD as a clock source for the peripheral clock muxes. * (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U) */ PSU_Mask_Write(CRL_APB_RPLL