北航电气实验FPGA程序

1、指令译码器
1）、程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity calculator is
port(a,b,c,data1,data2:in std_logic;
 dataout:out std_logic);
end calculator;
architecture calculator_arc of calculator is
signal cba:std_logic_vector(2 downto 0);
begin
cba<=c&b&a;
process(a,b,c,data1,data2)
begin
case cba is
when "001"=>dataout<=data1 and data2;
when "010"=>dataout<=data1 or data2;
when "011"=>dataout<=data1 nand data2;
when "100"=>dataout<=data1 xor data2;
when "101"=>dataout<=data1 xnor data2;
when others=>dataout<='0';
end case;
end process;
end;

2\




library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity state_stepper_b is
port(
     cp :in std_logic;
     dir:in std_logic;
     op :out std_logic_vector(3 downto 0)
    
     );
end state_stepper_b;

architecture a of state_stepper_b is
  type state is(s0,s1,s2,s3);
  attribute enum_encoding :string;
  attribute enum_encoding of
  state: type is"0001,0010,0100,1000";
 
  signal presentstate : state;
  signal nextstate :state;
begin
  
  switchtonextstate:process(cp)
  begin  
       if cp'event and cp='1' then