/**
******************************************************************************
* @file stm32f10x_tim.c
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file provides all the TIM firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_tim.h"
#include "stm32f10x_rcc.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup TIM
* @brief TIM driver modules
* @{
*/
/** @defgroup TIM_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup TIM_Private_Defines
* @{
*/
/* ---------------------- TIM registers bit mask ------------------------ */
#define CR1_CEN_Set ((uint16_t)0x0001)
#define CR1_CEN_Reset ((uint16_t)0x03FE)
#define CR1_UDIS_Set ((uint16_t)0x0002)
#define CR1_UDIS_Reset ((uint16_t)0x03FD)
#define CR1_URS_Set ((uint16_t)0x0004)
#define CR1_URS_Reset ((uint16_t)0x03FB)
#define CR1_OPM_Reset ((uint16_t)0x03F7)
#define CR1_CounterMode_Mask ((uint16_t)0x038F)
#define CR1_ARPE_Set ((uint16_t)0x0080)
#define CR1_ARPE_Reset ((uint16_t)0x037F)
#define CR1_CKD_Mask ((uint16_t)0x00FF)
#define CR2_CCPC_Set ((uint16_t)0x0001)
#define CR2_CCPC_Reset ((uint16_t)0xFFFE)
#define CR2_CCUS_Set ((uint16_t)0x0004)
#define CR2_CCUS_Reset ((uint16_t)0xFFFB)
#define CR2_CCDS_Set ((uint16_t)0x0008)
#define CR2_CCDS_Reset ((uint16_t)0xFFF7)
#define CR2_MMS_Mask ((uint16_t)0xFF8F)
#define CR2_TI1S_Set ((uint16_t)0x0080)
#define CR2_TI1S_Reset ((uint16_t)0xFF7F)
#define CR2_OIS1_Reset ((uint16_t)0x7EFF)
#define CR2_OIS1N_Reset ((uint16_t)0x7DFF)
#define CR2_OIS2_Reset ((uint16_t)0x7BFF)
#define CR2_OIS2N_Reset ((uint16_t)0x77FF)
#define CR2_OIS3_Reset ((uint16_t)0x6FFF)
#define CR2_OIS3N_Reset ((uint16_t)0x5FFF)
#define CR2_OIS4_Reset ((uint16_t)0x3FFF)
#define SMCR_SMS_Mask ((uint16_t)0xFFF8)
#define SMCR_ETR_Mask ((uint16_t)0x00FF)
#define SMCR_TS_Mask ((uint16_t)0xFF8F)
#define SMCR_MSM_Reset ((uint16_t)0xFF7F)
#define SMCR_ECE_Set ((uint16_t)0x4000)
#define CCMR_CC13S_Mask ((uint16_t)0xFFFC)
#define CCMR_CC24S_Mask ((uint16_t)0xFCFF)
#define CCMR_TI13Direct_Set ((uint16_t)0x0001)
#define CCMR_TI24Direct_Set ((uint16_t)0x0100)
#define CCMR_OC13FE_Reset ((uint16_t)0xFFFB)
#define CCMR_OC24FE_Reset ((uint16_t)0xFBFF)
#define CCMR_OC13PE_Reset ((uint16_t)0xFFF7)
#define CCMR_OC24PE_Reset ((uint16_t)0xF7FF)
#define CCMR_OC13M_Mask ((uint16_t)0xFF8F)
#define CCMR_OC24M_Mask ((uint16_t)0x8FFF)
#define CCMR_OC13CE_Reset ((uint16_t)0xFF7F)
#define CCMR_OC24CE_Reset ((uint16_t)0x7FFF)
#define CCMR_IC13PSC_Mask ((uint16_t)0xFFF3)
#define CCMR_IC24PSC_Mask ((uint16_t)0xF3FF)
#define CCMR_IC13F_Mask ((uint16_t)0xFF0F)
#define CCMR_IC24F_Mask ((uint16_t)0x0FFF)
#define CCMR_Offset ((uint16_t)0x0018)
#define CCER_CCE_Set ((uint16_t)0x0001)
#define CCER_CCNE_Set ((uint16_t)0x0004)
#define CCER_CC1P_Reset ((uint16_t)0xFFFD)
#define CCER_CC2P_Reset ((uint16_t)0xFFDF)
#define CCER_CC3P_Reset ((uint16_t)0xFDFF)
#define CCER_CC4P_Reset ((uint16_t)0xDFFF)
#define CCER_CC1NP_Reset ((uint16_t)0xFFF7)
#define CCER_CC2NP_Reset ((uint16_t)0xFF7F)
#define CCER_CC3NP_Reset ((uint16_t)0xF7FF)
#define CCER_CC1E_Set ((uint16_t)0x0001)
#define CCER_CC1E_Reset ((uint16_t)0xFFFE)
#define CCER_CC1NE_Reset ((uint16_t)0xFFFB)
#define CCER_CC2E_Set ((uint16_t)0x0010)
#define CCER_CC2E_Reset ((uint16_t)0xFFEF)
#define CCER_CC2NE_Reset ((uint16_t)0xFFBF)
#define CCER_CC3E_Set ((uint16_t)0x0100)
#define CCER_CC3E_Reset ((uint16_t)0xFEFF)
#define CCER_CC3NE_Reset ((uint16_t)0xFBFF)
#define CCER_CC4E_Set ((uint16_t)0x1000)
#define CCER_CC4E_Reset ((uint16_t)0xEFFF)
#define BDTR_MOE_Set ((uint16_t)0x8000)
#define BDTR_MOE_Reset ((uint16_t)0x7FFF)
/**
* @}
*/
/** @defgroup TIM_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup TIM_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup TIM_Private_FunctionPrototypes
* @{
*/
static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
uint16_t TIM_ICFilter);
static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
uint16_t TIM_ICFilter);
static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
uint16_t TIM_ICFilter);
static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
uint16_t TIM_ICFilter);
/**
* @}
*/
/** @defgroup TIM_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup TIM_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup TIM_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup TIM_Private_Functions
* @{
*/
/**
* @brief Deinitializes the TIMx peripheral registers to their default
* reset values.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @retval : None
*/
void TIM_DeInit(TIM_TypeDef* TIMx)
{
/* Check the parameters */
assert_param(IS_TIM_ALL_PERIPH(TIMx));
switch (*(uint32_t*)&TIMx)
{
case TIM1_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
break;
case TIM2_BASE:
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
break;
case TIM3_BASE:
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
break;
case TIM4_BASE:
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
break;
case TIM5_BASE:
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
break;
case TIM6_BASE:
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
break;
case TIM7_BASE:
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
break;
case TIM8_BASE:
RCC_APB2PeriphResetCmd(RCC_A
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bsp_pwm_output.c 5KB
stm32f10x_dbgmcu.c 4KB
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stm32f10x_crc.c 3KB
main.c 2KB
stm32f10x_tim.crf 268KB
adxl345.crf 258KB
stm32f10x_rcc.crf 255KB
stm32f10x_i2c.crf 253KB
main.crf 253KB
usart1.crf 253KB
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stm32f10x_gpio.crf 251KB
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bsp_pwm_output.crf 248KB
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bsp_pwm_output.d 743B
stm32f10x_gpio.d 733B
stm32f10x_i2c.d 718B
stm32f10x_rcc.d 718B
stm32f10x_tim.d 718B
main.d 717B
usart1.d 710B
system_stm32f10x.d 696B
stm32f10x_it.d 693B
adxl345.d 671B
core_cm3.d 99B
startup_stm32f10x_hd.d 75B
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STM32-DEMO_USART1-DEMO.dep 8KB
STM32-DEMO.uvgui.Fly 132KB
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stm32f10x_tim.h 48KB
core_cm3.h 41KB
stm32f10x_adc.h 19KB
stm32f10x_dma.h 18KB
stm32f10x_sdio.h 18KB
stm32f10x_fsmc.h 17KB
stm32f10x_i2c.h 17KB
stm32f10x_rcc.h 16KB
stm32f10x_gpio.h 15KB
stm32f10x_spi.h 15KB
stm32f10x_usart.h 14KB
stm32f10x_flash.h 14KB
stm32f10x_can.h 14KB
stm32f10x_dac.h 10KB
stm32f10x_bkp.h 7KB
stm32f10x_exti.h 6KB
misc.h 5KB
stm32f10x_pwr.h 4KB
stm32f10x_iwdg.h 4KB
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