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LA∥ 6. 1 Operational Registers ■重日口 6 6.1.1 Ro(Indirect Address Register) 6.1. 2 R1 (Time Clock/Counter) 6 6.1.3 R2(Program Counter)and Stack Data Memory Configuration............ 6.1.4 R3(Status Register) 6.1.5 R4 (RAM Select Register) 6.1.6 Bank 0 R5 -R7(Port 5- port 7) 10 6.1.7 Bank O R8(AISR: ADC Input Select Register) 6.1.8 Bank O R9(ADCON: ADC Control Register) 12 6.1. 9 Bank O RA (ADOC: ADC Offset Calibration Register) 13 6.1.10 Bank O RB(ADDATA: Converted Value of ADC) 14 6.1.11 Bank O RC (ADDATA1H: Converted Value of ADC) 14 6.1.12 Bank O RD(ADDATA1L: Converted Value of ADC) 15 6.1.13 Bank 0 RE(Interrupt Status 2 and Wake-up Control Register) 15 6.1.14 BankO RF(Interrupt Status 2 Register) 16 6.1.15 Bank 1 R5(TBHP: Table Point Register for Instruction T BRD) 17 6.1.16 Bank 1 R6(TBLP: Table Point Register for Instruction TBRD) 17 6.1.17 Bank 1 R7(PWMCON: PWM Control Register) 6. 1.18 Bank 1 R& (TMRCON: Timer Control Register) 18 6.1.19 Bank 1 R9(PRD1: PWM1 Time Period) 6.1. 20 Bank 1 RA(PRD2: PWM2 Time Period) 19 6.1.21 Bank 1 RB(DT1: PWM1 Duty Cycle) 19 6.1.22 Bank 1 RC (DT2: PWM2 Duty Cycle) 19 6.1.23 Bank 1 RE (LVD Interrupt and Wake-up Register 6. 1.24 Bank 1 RF (System Control Register) 20 6.1.25R10~R3F 24 6.2 Special Purpose registers .24 621A( Accumulator)…… 24 6.22CONT( Control Register)…… 24 6. 2. 3 l0C50-lOC70(10 Port Control Register) .25 624Oc80( Comparator Control Register)…… 25 6.2.5 I0C90(TMR1: PWM1 Timer) 26 LAW 6.2.6 IOCAO (TMR2: PWM2 Timer) 26 6.2.7 lOCB0(Pull-down Control Register 26 6.2.8 lOCC0(Open-drain Control Register) 26 6.2.9 lOCO(Pull-high Control Register) 27 6. 2. 10 IOCEO(WDT Control Register and Interrupt Mask Register 2) 6.2.11 lOCF0 (Interrupt Mask Register) 28 6.2. 12 IOC51(High Sink Control Register 1) 6.2.13 0C61(High Sink Control Register 2) 29 62.14OC71( High Driver Control Register1)…… 6. 2.15 IOC81(High Driver Control Register 2) 30 6.2.16 IOCF1(Pull-high Control Register) 6.3 TCC/DT and Prescaler 6.4 /0 Ports 6.4.1 Usage of Port 5 Input Change Wake-up/Interrupt Function 35 6.5 Reset and Wake-up 35 6.5.1 Reset and Wake-up Operation Wake-up and Interrupt Modes Operation Summary Register Initial Values after Reset 40 Controller Reset Block Diagram 45 6.5.2 T and P status under the Status Register....... 45 6.6 Interrupt .46 6.7 Analog-to-Digital Converter(ADC) …48 6.7.1 ADC Control Register(AISR/R8, ADCON/R9, ADOC/RA) Bank 0 R8(AISR: ADC Input Select Register) 49 Bank O R9(ADCON: ADC Control Register) 6.7.1. 3 RA (ADOC: AD Offset Calibration Register) 6.7.1. 4 Bank 1 RF (IRC Switch Register) 52 6.7.2 ADC Data Register(ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD) 6.7.3 ADC Sampling Time 52 6.7.4 AD Conversion time 52 6.7.5 ADC Operation during Sleep Mode 53 6.7.6 Programming Process/Consideration Programming Process Sample demo programs 54 6.8 Dual sets of pwm( Pulse width modulation).……,……………56 6.8.1 Overview 6.8.2 Increment Timer Counter (TMRX: TMR1 or TMR2) 57 6.8. 3 PWM Time Period (TMRX: TMR1 or TMR2) 57 6.8.4 PWM Duty Cycle(DTX: DT1 or DT2; DLX: DL1 or DL2 57 685 Comparator×…… 58 6.8.6 PWM Programming process/Steps 58 LAW 6.9Tmer/ Counter.… 58 6.9.1 Overview 6.9.2 Functional Description 59 6.9.3 Programming the related Registers….….….….….…...…..159 6.9. 4 Timer Programming Process/Steps 60 6. 10 Comparator.... 60 6.10.1 External Reference Signal .60 6.10.2 Comparator Outputs 6. 10.3 Using Comparator as an Operation Amplifier 6.10.4 Comparator Interrupt 61 6. 10.5 Wake-up from Sleep Mode 6.11 Oscillator.… .62 6.11.1 Oscillator modes 62 6.11.2 Crystal Oscillator/Ceramic Resonators(Crystal) 6.113 External rc oscillator mode 6.11 4 Internal rc oscillator mode 6.12 Power-on Considerations 68 6.12.1 Programmable Wdt Time-out Period 68 6.12.2 External Power-on reset circuit 6.12.3 Residual Voltage protection .69 6.13 Code option… 70 6.13. 1 Code Option Register(Word O) 70 6.13.2 Code Option Register(Word 1) 6133 Customer| D Register(Word2)…… 73 6. 14 Low Voltage Detector/Low Voltage Reset 6.14.1 Voltage Reset 74 6.14.2 Low Voltage Detector 74 Bank 1 RE(LVD Interrupt and Wake-up Register)..........74 6.1422Bank0RE( Interrupt Status2 and Wake-up Control Register)………175 6.14.3 Programming Process......,.,.,,…,… 76 6.15 Instruction set 77 8. 1 AD Converter characteristics 81 8.2 Comparator Characteristics 82 8. 3 OP Characteristics 82 8.4 VREF 2V/3V/4V Characteristics 83 LAW B.1EM78P372ND14 B.2EM78P372NS014 88 B 3 EM78P372NSO16A 89 B.4EM78P372ND18 90 B 5 EM78P372NSO18 91 B.6EM78P372ND20 92 B7 EM78P372NSO20 93 B 8 Em78P372NSS20 4 B 9 EM78P372NMS10 95 B10 EM78P372NSS10 96 C 1 Address Trap detect 97 0.9 Preliminary version 2010/06/21 0. Preliminary version 201007/19 Modified the lOCCO Control Register 0.92 Modified the Bank 1-RF[3: 0] Control Reigster 2010/08/06 Modified the Bank 0-RA[2: 0] Control Reigster Initial version 1.0 2010/12/10 Modified the Operating frequency range (DC 16 MHz 1. Modified the electrical characteristics 2. Modified the Quality Assurance and Reliability section in the 2011/05/24 Appendix LAA The EM78P372N is an B-bit microprocessor designed and developed with low-power and high-speed CMOS technology. The device has an on-chip 2Kx 13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user's OTP memory code. Three Code option bits are also available to meet user's requirements With enhanced OTP-ROM features, the EM78P372N provides a convenient way of developing and verifying users programs. Moreover, this otP device offers the advantages of easy and effective program updates, using development and programming tools User can avail of the elan Writer to easily program his development code ■ CPU configuration Fast set-up time requires only 0.8ms (VDD: 5V 2K×13 bits on- chip rom Crystal: 4 MHz, C1/C2: 15pF)in XT mode and 10us in 80x8 bits on-chip registers(SRAM) IRC mode(vDD: 5V,IRC: 4 MHz) 8-level stacks for subroutine nesting Peripheral configuration 4 programmable Level Voltage Detector 8-bit real time clock/counter (TCC)with selective (LVD):4.5V,4.0V3.3V,22V signal sources, trigger edges, and overflow interrupt 3 programmable Level Voltage Reset 8-bit multi-channel Analog-to-Digital Converter with (LvR):4.0V,3.5V,2.7V 12-bit resolution in Vref mode Less than 1.5 mA at 5V/4 MHz One pair of comparator or oP(offset voltage: smaller Typically 15 HA, at 3 V/32kHz Typically 2 HA, during sleep mode Two Pulse Width Modulation(PWM)with 8-bit resolution 3 bidirectional l/o ports: P5, P6, P7 Ten available interrupts ·18/ O pins · TCC overflow interrupt Wake-up port: P5 Input-port status changed interrupt ( wake up from 8 programmable pull- down I/o pins sleep mode External interrupt 16 programmable pull-high IO pins ADC completion interrupt 8 programmable open-drain 1/0 pins Comparator status change interrupt 14 programmable high-sink current IO pins Low voltage detect (LVD)interrupt External interrupt: P60 PWM1-2 period match interrupt a Operating voltage rang PWM1-2 duty match interrupt 2. 1V-55V at 0C-70C(commercial) ■ Special Features 2.3V-55V at-40 C-85C (industrial) Programmable free running Watchdog Timer (45ms:18ms) Operating frequency range(base on 2 clocks) Power saving Sleep mode Crystal mode: DC-16 MHZ, 4.5V, Power-on voltage detector available(1. 9v+0.2V DC N8 MHz. 3V: DC 4 MHz. 2.1V High EFT immunity(better performance at 4 MHz or ERC mode: DC-2 MHz. 2.1V below IRC mode Package Type Oscillation mode: 16 MHz. 4 MHz. 1 MHz. 8 MHz 10-pin MSOP 118mil EM78P372NMS10J/S 10-pin SSoP 150mil EM78P372NSS1OJ/S 4-pin DIP 300mil EM78P372ND14J/S 14-pin SoP 150mil EM78P372NSO14J/S 16-pin SOP 150mil ±2%5% EM78P372NSO1GAJ/S 4 MHZ ±2% ±1% 18-pin DIP 300mil EM78P372ND18J/S 16 MHZ ±2% ±1% ±2%±5% 18-pin SOP 300mil EM78P372NSO18J/S 8 MHz ±1% ±2% 20-pin DIP 300mil EM78P372ND20J/S 1 MHz ±1% ±2%±5% 20 pin soP 300mil EM78P372NSO20J/S All the four main frequencies can be trimmed by 20 pin SSOP 209mil EM78P372NSS2OJ/S programming with six calibrated bits in the ICE300N These are Green products that do not contain Simulator. OTP is auto trimmed by elan Writer hazardous substances (This specification is subject to change without further notice) 4∥ P52ADC2 16□P5M/ ADC1/PWM2 P52/ADC2 P51/ADC1/PMW2 P53/ADC312 m 13 P50/ADCO 两5AD3中2里15 P54TCCNREF P54 /TCCVREF口312□P55ADc6 Sco/ERIn go 14 P55/ADC6/OSCO/ERCIn P71/RESET4 13P70VADC5/OSCVRCOUT P71/RESET|4 11 P70/ADC5/OSCURCOUT 2 121VDD vss「5 60/NT d1口P67 ADCA/PWM1 9 P67/ADC4/PWM1 10|P66CN 8□P66cN P4c0□8 91P65c|N Figure 3-1 EM78P372ND 14/S014 Figure 3-2 EM78P372NSO16A P52ADC2 187]P51/ADC1/PWM2 P56 2q P57/ADC7 P53/ADC3 17 P50VADCO 19 P51/ADC1PWN2 P54/TCCWREF 3 16 P55/ADC6/OSCOERCn P53/ P50ADCO P/1/RESET□4曾15 P7O/ADCS/OSCIRCOUT P54 TCC/REF□4 17■P55/ADc6Sco/ERci P71/ RESET「5 16■P7O∥ADC5/ SCVRCOUT vss「5 14VDD 60/NT6 O 13 P67/ADCA/PWM1 P60//NT P67/ADCA/PWM1 g12□P6C|N 8 13 P66/CIN- 11F65c№ P62 9 P65 10P4c0 P63□10 11 P64/CO Figure 3-3 EM78P372ND18/018 Figure 3-4 EM78P372ND20/S020/SS20 P51ADC1/PWM2 10□P50/ADc0 P52ADC2 9P55/ADC6/OSCOERC P53ADC3 8□P7MADc5 /OSCIRCOUT P71/RESET) 4 Vs□5 6□P67ADG4PW Figure 3-5 EM78P372NMS10/SS10 (This specification is subject to change without further notice) LAA Bidirectional lo pin with programmable P50 STCMOS pull-down, pull-high and pin change P50 wake-up ADCO AN ADC Input O Bidirectional 1/0 pin with programmable P51 ST CMOS pull-down, pull-high, high-driver, high-sink and pin change wake-up ADC 1 AN ADC Input 1 PWM2 CMOS PWM2 output Bidirectional 10 pin with programmable P52 ST CMOS pull-down, pull-high, high-driver, high-sink P52 and pin change wake-up ADC2 AN ADC Input 2 Bidirectional i/o pin with programmable P53 STCMOS pull-down, pull-high, high-driver, high-sink P53 and pin change wake-up ADC3 AN ADC Input 3 Bidirectional w/O pin with programmable P54 ST CMOS pull-down, pull-high, high-driver, high-sink P5 and pin change wake-up TCC ST I Real Time Clock/ Counter clock input VREF AN ADC external voltage reference Bidirectional i /O pin with programmable P55 ST CMOS pull-down, pull-high and pin change ake P55 ADC6 AN ADC Input 6 OSCO XTAL Clock output of crystal/ resonator oscillator ERCin AN External Rc input pin Bidirectional lo pin with programmable P56 P56 ST CMOS pull-down, pull-high, high-driver, high-sink and pin change wake-up Bidirectional l/0 pin with programmable P57 ST CMOS pull-down, pull-high, high-driver, high-sink P57 and hange wake ADC7 ST ADC Input 7 Bidirectional l/o pin with programmable P60 CMOS open-drain, pull-high, high-driver and high P60//NT /INT ST External interrupt pin (This specification is subject to change without further notice) LAW Bidirectional l/0 pins with programmable P61~P63 P61-P63 ST CMOSopen-drain, pull-high, high-driver and high sink Bidirectional l0 pins with programmable CMOS open-drain, pull-high, high-driver and hig 64/CO sink CO ST Comparator output Bidirectional /0 pins with programmable P65 ST CMOS open-drain, pull-high, high-driver and high P65/CIN+ sink CIN+ ST Non-inverting end of comparator Bidirectional l/0 pins with programmable P66 ST CMOS open-drain, pull-high, high-driver and high P66/CIN CIN- ST Inverting end of comparator Bidirectional 10 pins with programmable 67 CMOS open-drain, pull-high, high-driver and high sink P67/ADCA/PWM1 ADC AN ADC Input 4 PWM1 CMOS PWM1 output P70 P70 Bidirectional l/0 pin ADCs AN ADC Input 5 P70/ADC5/OSCH OSCI XTAL Clock input of crystal/ resonator oscillator RCOUT Clock output of internal rc oscillator ROCUT CMos Clock output of external rc oscillator (open-drain P71 ST CMOS Bidirectional I/O pin(open-drain) System reset pin /RESET ST (should be external pull-high) VDD VDD Power VSS Power Ground ST: Schmitt Trigger input AN: analog pin TAL: oscillation pin for crystal/resonator CMOS: CMOS output (This specification is subject to change without further notice)

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