AM335x Sitara™ Processors
Technical Reference Manual
Literature Number: SPRUH73L
October 2011–Revised February 2015
Contents
Preface..................................................................................................................................... 170
1 Introduction ..................................................................................................................... 172
1.1 AM335x Family............................................................................................................ 172
1.1.1 Device Features.................................................................................................. 172
1.1.2 Device Identification ............................................................................................. 173
1.1.3 Feature Identification ............................................................................................ 173
2 Memory Map .................................................................................................................... 177
2.1 ARM Cortex-A8 Memory Map........................................................................................... 177
3 ARM MPU Subsystem ....................................................................................................... 186
3.1 ARM Cortex-A8 MPU Subsystem ...................................................................................... 187
3.1.1 Features........................................................................................................... 188
3.1.2 MPU Subsystem Integration.................................................................................... 188
3.1.3 MPU Subsystem Clock and Reset Distribution .............................................................. 189
3.1.4 ARM Subchip..................................................................................................... 192
3.1.5 Interrupt Controller............................................................................................... 193
3.1.6 Power Management ............................................................................................. 194
3.1.7 ARM Programming Model ...................................................................................... 196
4 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-
ICSS)............................................................................................................................... 198
4.1 Introduction ................................................................................................................ 199
4.1.1 Features........................................................................................................... 200
4.2 Integration.................................................................................................................. 201
4.2.1 PRU-ICSS Connectivity Attributes............................................................................. 202
4.2.2 PRU-ICSS Clock and Reset Management ................................................................... 202
4.2.3 PRU-ICSS Pin List............................................................................................... 203
4.2.4 PRU-ICSS Internal Pinmux..................................................................................... 204
4.3 PRU-ICSS Memory Map Overview..................................................................................... 206
4.3.1 Local Memory Map .............................................................................................. 206
4.3.2 Global Memory Map............................................................................................. 207
4.4 Functional Description.................................................................................................... 208
4.4.1 PRU Cores........................................................................................................ 208
4.4.2 Interrupt Controller (INTC)...................................................................................... 225
4.4.3 Industrial Ethernet Peripheral (IEP) ........................................................................... 232
4.4.4 Universal Asynchronous Receiver/Transmitter (UART) .................................................... 235
4.4.5 ECAP .............................................................................................................. 248
4.5 Registers................................................................................................................... 249
4.5.1 PRU_ICSS_PRU_CTRL Registers............................................................................ 249
4.5.2 PRU_ICSS_PRU_DEBUG Registers ......................................................................... 259
4.5.3 PRU_ICSS_INTC Registers.................................................................................... 324
4.5.4 PRU_ICSS_IEP Registers...................................................................................... 388
4.5.5 PRU_ICSS_UART Registers................................................................................... 408
4.5.6 PRU_ICSS_ECAP Registers................................................................................... 427
4.5.7 PRU_ICSS_CFG Registers .................................................................................... 427
5 Graphics Accelerator (SGX) ............................................................................................... 444
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5.1 Introduction ................................................................................................................ 445
5.1.1 POWERVR SGX Main Features............................................................................... 445
5.1.2 SGX 3D Features................................................................................................ 446
5.1.3 Universal Scalable Shader Engine (USSE) – Key Features ............................................... 447
5.1.4 Unsupported Features .......................................................................................... 447
5.2 Integration.................................................................................................................. 448
5.2.1 SGX530 Connectivity Attributes ............................................................................... 448
5.2.2 SGX530 Clock and Reset Management...................................................................... 448
5.2.3 SGX530 Pin List ................................................................................................. 449
5.3 Functional Description.................................................................................................... 450
5.3.1 SGX Block Diagram ............................................................................................. 450
5.3.2 SGX Elements Description ..................................................................................... 450
6 Interrupts......................................................................................................................... 452
6.1 Functional Description.................................................................................................... 453
6.1.1 Interrupt Processing ............................................................................................ 454
6.1.2 Register Protection .............................................................................................. 455
6.1.3 Module Power Saving........................................................................................... 455
6.1.4 Error Handling.................................................................................................... 455
6.1.5 Interrupt Handling................................................................................................ 455
6.2 Basic Programming Model............................................................................................... 456
6.2.1 Initialization Sequence .......................................................................................... 456
6.2.2 INTC Processing Sequence.................................................................................... 456
6.2.3 INTC Preemptive Processing Sequence ..................................................................... 460
6.2.4 Interrupt Preemption............................................................................................. 464
6.2.5 ARM A8 INTC Spurious Interrupt Handling .................................................................. 464
6.3 ARM Cortex-A8 Interrupts ............................................................................................... 465
6.4 PWM Events............................................................................................................... 469
6.5 Interrupt Controller Registers............................................................................................ 470
6.5.1 INTC Registers................................................................................................... 470
7 Memory Subsystem .......................................................................................................... 516
7.1 GPMC ...................................................................................................................... 517
7.1.1 Introduction ....................................................................................................... 517
7.1.2 Integration......................................................................................................... 520
7.1.3 Functional Description........................................................................................... 522
7.1.4 GPMC High-Level Programming Model Overview .......................................................... 601
7.1.5 Use Cases ........................................................................................................ 612
7.1.6 GPMC Registers ................................................................................................. 622
7.2 OCMC-RAM ............................................................................................................... 820
7.2.1 Introduction ....................................................................................................... 820
7.2.2 Integration......................................................................................................... 821
7.3 EMIF........................................................................................................................ 822
7.3.1 Introduction ....................................................................................................... 822
7.3.2 Integration......................................................................................................... 824
7.3.3 Functional Description........................................................................................... 826
7.3.4 Use Cases ........................................................................................................ 844
7.3.5 EMIF4D Registers ............................................................................................... 844
7.3.6 DDR2/3/mDDR PHY Registers ................................................................................ 888
7.4 ELM......................................................................................................................... 897
7.4.1 Introduction ....................................................................................................... 897
7.4.2 Integration......................................................................................................... 898
7.4.3 Functional Description........................................................................................... 899
7.4.4 Basic Programming Model...................................................................................... 902
7.4.5 ELM Registers.................................................................................................... 907
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8 Power, Reset, and Clock Management (PRCM) ................................................................... 1112
8.1 Power, Reset, and Clock Management .............................................................................. 1113
8.1.1 Introduction ..................................................................................................... 1113
8.1.2 Device Power-Management Architecture Building Blocks ............................................... 1113
8.1.3 Clock Management ............................................................................................ 1113
8.1.4 Power Management ........................................................................................... 1119
8.1.5 PRCM Module Overview ..................................................................................... 1130
8.1.6 Clock Generation and Management ......................................................................... 1132
8.1.7 Reset Management ............................................................................................ 1148
8.1.8 Power-Up/Down Sequence ................................................................................... 1156
8.1.9 IO State.......................................................................................................... 1157
8.1.10 Voltage and Power Domains ................................................................................ 1157
8.1.11 Device Modules and Power Management Attributes List ............................................... 1158
8.1.12 Clock Module Registers ...................................................................................... 1161
8.1.13 Power Management Registers .............................................................................. 1315
9 Control Module ............................................................................................................... 1355
9.1 Introduction............................................................................................................... 1356
9.2 Functional Description .................................................................................................. 1356
9.2.1 Control Module Initialization................................................................................... 1356
9.2.2 Pad Control Registers ......................................................................................... 1356
9.2.3 EDMA Event Multiplexing ..................................................................................... 1357
9.2.4 Device Control and Status .................................................................................... 1358
9.2.5 DDR PHY........................................................................................................ 1364
9.3 Registers ................................................................................................................. 1365
9.3.1 CONTROL_MODULE Registers ............................................................................. 1365
10 Interconnects ................................................................................................................. 1468
10.1 Introduction............................................................................................................... 1469
10.1.1 Terminology.................................................................................................... 1469
10.1.2 L3 Interconnect ................................................................................................ 1469
10.1.3 L4 Interconnect ................................................................................................ 1472
11 Enhanced Direct Memory Access (EDMA).......................................................................... 1473
11.1 Introduction............................................................................................................... 1474
11.1.1 EDMA3 Controller Block Diagram .......................................................................... 1474
11.1.2 Third-Party Channel Controller (TPCC) Overview ........................................................ 1475
11.1.3 Third-Party Transfer Controller (TPTC) Overview ........................................................ 1476
11.2 Integration ................................................................................................................ 1477
11.2.1 Third-Party Channel Controller (TPCC) Integration ...................................................... 1477
11.2.2 Third-Party Transfer Controller (TPTC) Integration....................................................... 1478
11.3 Functional Description .................................................................................................. 1480
11.3.1 Functional Overview .......................................................................................... 1480
11.3.2 Types of EDMA3 Transfers .................................................................................. 1483
11.3.3 Parameter RAM (PaRAM) ................................................................................... 1485
11.3.4 Initiating a DMA Transfer..................................................................................... 1497
11.3.5 Completion of a DMA Transfer .............................................................................. 1500
11.3.6 Event, Channel, and PaRAM Mapping..................................................................... 1501
11.3.7 EDMA3 Channel Controller Regions ....................................................................... 1503
11.3.8 Chaining EDMA3 Channels.................................................................................. 1505
11.3.9 EDMA3 Interrupts ............................................................................................. 1506
11.3.10 Memory Protection .......................................................................................... 1512
11.3.11 Event Queues ................................................................................................ 1516
11.3.12 EDMA3 Transfer Controller (EDMA3TC) ................................................................. 1518
11.3.13 Event Dataflow ............................................................................................... 1521
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11.3.14 EDMA3 Prioritization ........................................................................................ 1521
11.3.15 EDMA3 Operating Frequency (Clock Control)........................................................... 1522
11.3.16 Reset Considerations ....................................................................................... 1522
11.3.17 Power Management ......................................................................................... 1522
11.3.18 Emulation Considerations .................................................................................. 1522
11.3.19 EDMA Events ................................................................................................ 1540
11.4 EDMA3 Registers ....................................................................................................... 1543
11.4.1 EDMA3CC Registers ......................................................................................... 1543
11.4.2 EDMA3TC Registers.......................................................................................... 1678
11.5 Appendix A............................................................................................................... 1731
11.5.1 Debug Checklist ............................................................................................... 1731
11.5.2 Miscellaneous Programming/Debug Tips .................................................................. 1732
11.5.3 Setting Up a Transfer......................................................................................... 1734
12 Touchscreen Controller ................................................................................................... 1736
12.1 Introduction............................................................................................................... 1737
12.1.1 TSC_ADC Features........................................................................................... 1737
12.1.2 Unsupported TSC_ADC_SS Features ..................................................................... 1737
12.2 Integration ................................................................................................................ 1738
12.2.1 TSC_ADC Connectivity Attributes .......................................................................... 1738
12.2.2 TSC_ADC Clock and Reset Management................................................................. 1739
12.2.3 TSC_ADC Pin List ............................................................................................ 1739
12.3 Functional Description .................................................................................................. 1740
12.3.1 Hardware-Synchronized or Software-Enabled ............................................................ 1740
12.3.2 Open Delay and Sample Delay ............................................................................. 1740
12.3.3 Averaging of Samples (1, 2, 4, 8, and 16) ................................................................. 1740
12.3.4 One-Shot (Single) or Continuous Mode ................................................................... 1740
12.3.5 Interrupts ....................................................................................................... 1740
12.3.6 DMA Requests ................................................................................................ 1741
12.3.7 Analog Front End (AFE) Functional Block Diagram ..................................................... 1741
12.4 Operational Modes...................................................................................................... 1743
12.4.1 PenCtrl and PenIRQ .......................................................................................... 1744
12.5 Touchscreen Controller Registers .................................................................................... 1747
12.5.1 TSC_ADC_SS Registers..................................................................................... 1747
13 LCD Controller................................................................................................................ 1829
13.1 Introduction............................................................................................................... 1830
13.1.1 Purpose of the Peripheral .................................................................................... 1830
13.1.2 Features ........................................................................................................ 1831
13.2 Integration ................................................................................................................ 1832
13.2.1 LCD Controller Connectivity Attributes ..................................................................... 1832
13.2.2 LCD Controller Clock and Reset Management............................................................ 1833
13.2.3 LCD Controller Pin List ....................................................................................... 1833
13.3 Functional Description .................................................................................................. 1834
13.3.1 Clocking ........................................................................................................ 1834
13.3.2 LCD External I/O Signals..................................................................................... 1836
13.3.3 DMA Engine ................................................................................................... 1837
13.3.4 LIDD Controller ................................................................................................ 1838
13.3.5 Raster Controller .............................................................................................. 1840
13.3.6 Interrupt Conditions ........................................................................................... 1852
13.3.7 DMA............................................................................................................. 1854
13.3.8 Power Management .......................................................................................... 1854
13.4 Programming Model .................................................................................................... 1855
13.4.1 LCD Character Displays...................................................................................... 1855
13.4.2 Active Matrix Displays ........................................................................................ 1858
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SPRUH73L–October 2011–Revised February 2015 Contents
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