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### AM335x 参考手册概览与关键技术知识点 #### 一、引言 AM335x是一款由德州仪器(TI)推出的高性能嵌入式处理器系列，该系列处理器基于ARM Cortex-A8内核，并集成了多种高级功能模块，如可编程实时单元(PRUs)、内存控制器等。本手册旨在详细介绍AM335x系列处理器的技术规格和使用方法，为设计人员提供全面的硬件和软件开发指南。 #### 二、AM335x 家族特性 ##### 2.1 设备特点 AM335x家族具有以下显著特性： - **高性能ARM Cortex-A8内核**：支持先进的指令集，实现高效的应用处理能力。 - **集成多种外设接口**：包括高速USB、以太网MAC、SD/MMC、SPI、I2C等多种接口，便于构建复杂的系统架构。 - **可编程实时单元(PRUs)**：两个独立的32位RISC内核，用于实时任务处理，如电机控制、工业通信协议实现等。 - **丰富的内存管理选项**：支持多种类型的存储器，如DDR/DDR2/DDR3、SRAM、Flash等。 - **低功耗设计**：采用先进的工艺技术，支持多种节能模式，适用于移动设备和物联网应用。 ##### 2.2 硅片修订版功能差异与增强 AM335x的不同硅片修订版本之间存在一定的功能差异和改进，主要包括： - **添加RTC闹钟唤醒功能**：支持在深度睡眠模式下通过RTC闹钟唤醒设备。 - **修改引导加载程序标识符(BOOTP Identifier)**：更改了用于识别不同设备变体的标识符。 - **修改USB描述符中的产品字符串**：以更好地反映设备特性。 - **增加DPLL电源开关控制和状态寄存器**：提供了更精细的电源管理能力。 - **增加CORE SRAM LDO保留模式控制**：允许在低功耗模式下保持关键内存区域的数据。 - **增加GPMC_A9引脚复用选项**：增强了引脚复用灵活性，方便与其他接口协同工作。 - **改变输入信号nNMI(EXTINTn)极性**：提高了外部中断信号的兼容性和可靠性。 - **修改vtp_ctrl寄存器中的ncin和pci_n位默认值**：以适应新的设计需求。 - **修改RGMII模式下的内部延迟设置**：提供了更灵活的网络接口配置选项。 - **修改RGMII时钟源**：增加了时钟配置的灵活性。 - **改变确定EMAC启动期间操作速度的方法**：提高了启动效率。 - **添加EFUSE_SMA寄存器**：帮助识别不同的设备变体，简化了设备配置过程。 #### 三、内存映射与MPU子系统 ##### 3.1 ARM Cortex-A8 内存映射 - **描述**：详细介绍了AM335x中ARM Cortex-A8内核的内存布局，包括代码段、数据段、堆栈等的分配方式。 - **作用**：为开发人员提供了必要的信息，以便正确地配置内存区域，实现高效的程序执行。 ##### 3.2 ARM MPU子系统 - **功能**：ARM Cortex-A8 MPU子系统用于管理和保护内存区域，支持多级内存访问控制。 - **特点**： - **多级内存保护**：支持不同级别的访问权限设置，确保程序运行的安全性。 - **集成时钟和复位管理**：提供了统一的时钟和复位管理机制，简化了系统设计复杂度。 - **中断控制器**：集成的中断控制器支持复杂的中断处理逻辑，提高系统的响应速度。 - **电源管理**：支持多种节能模式，降低整体功耗。 #### 四、可编程实时单元(PRUs)和工业通信子系统(PRU-ICSS) ##### 4.1 PRU-ICSS概述 - **定义**：PRU-ICSS是一个高度集成的子系统，包含两个可编程实时单元(PRUs)，专门用于实时任务处理。 - **功能**：PRUs可以独立于主CPU运行，支持实时通信协议，如EtherCAT、CANopen等。 ##### 4.2 集成特性 - **连接属性**：描述了PRU-ICSS与其他系统组件之间的连接关系，包括GPIO、串行接口等。 - **时钟和复位管理**：提供了详细的时钟和复位管理机制，确保子系统的稳定运行。 - **内部引脚复用**：支持灵活的引脚配置，满足不同的应用场景需求。 ##### 4.3 PRU-ICSS内存映射 - **局部内存映射**：介绍了每个PRU的局部内存空间布局，包括代码存储区、数据存储区等。 - **全局内存映射**：描述了全局内存空间的分配情况，包括共享内存区域等。 ##### 4.4 功能描述 - **PRU核心**：每个PRU都包含一个32位RISC内核，支持自定义程序编写，实现复杂的功能。 - **中断控制器(INTC)**：负责处理来自PRUs的中断请求，确保实时任务能够及时响应。 AM335x是一款高度集成且功能强大的嵌入式处理器，适合应用于各种复杂的嵌入式系统设计中。通过对上述技术知识点的学习，开发人员可以更好地理解和利用AM335x的强大性能，开发出高质量的产品。
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AM335x and AMIC110 Sitara™ Processors
Technical Reference Manual
Literature Number: SPRUH73P
October 2011–Revised March 2017
2
SPRUH73P–October 2011–Revised March 2017
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Copyright © 2011–2017, Texas Instruments Incorporated
Contents
Contents
Preface..................................................................................................................................... 173
1 Introduction ..................................................................................................................... 174
1.1 AM335x Family............................................................................................................ 174
1.1.1 Device Features.................................................................................................. 174
1.1.2 Device Identification ............................................................................................. 174
1.2 Silicon Revision Functional Differences and Enhancements ....................................................... 174
1.2.1 Added RTC Alarm Wakeup for DeepSleep Modes.......................................................... 174
1.2.2 Changed BOOTP Identifier..................................................................................... 174
1.2.3 Changed Product String in USB Descriptor .................................................................. 175
1.2.4 Added DPLL Power Switch Control and Status Registers ................................................. 175
1.2.5 Added Control for CORE SRAM LDO Retention Mode..................................................... 175
1.2.6 Added Pin Mux Options for GPMC_A9 to Facilitate RMII Pin Muxing.................................... 175
1.2.7 Changed Polarity of Input Signal nNMI (Pin EXTINTn)..................................................... 175
1.2.8 Changed Default Value of ncin and pcin Bits in vtp_ctrl Register......................................... 176
1.2.9 Changed Default Value of RGMII Mode to No Internal Delay ............................................. 176
1.2.10 Changed Default Value of RMII Clock Source.............................................................. 176
1.2.11 Changed the Method of Determining Speed of Operation During EMAC Boot ........................ 176
1.2.12 Added EFUSE_SMA Register for Help Identifying Different Device Variants .......................... 176
2 Memory Map .................................................................................................................... 177
2.1 ARM Cortex-A8 Memory Map........................................................................................... 177
3 ARM MPU Subsystem ....................................................................................................... 186
3.1 ARM Cortex-A8 MPU Subsystem ...................................................................................... 187
3.1.1 Features........................................................................................................... 188
3.1.2 MPU Subsystem Integration.................................................................................... 188
3.1.3 MPU Subsystem Clock and Reset Distribution .............................................................. 189
3.1.4 ARM Subchip..................................................................................................... 192
3.1.5 Interrupt Controller............................................................................................... 193
3.1.6 Power Management ............................................................................................. 194
3.1.7 ARM Programming Model ...................................................................................... 196
4 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-
ICSS)............................................................................................................................... 198
4.1 Introduction ................................................................................................................ 199
4.1.1 Features........................................................................................................... 200
4.2 Integration.................................................................................................................. 201
4.2.1 PRU-ICSS Connectivity Attributes............................................................................. 202
4.2.2 PRU-ICSS Clock and Reset Management ................................................................... 202
4.2.3 PRU-ICSS Pin List............................................................................................... 203
4.2.4 PRU-ICSS Internal Pinmux..................................................................................... 204
4.3 PRU-ICSS Memory Map Overview..................................................................................... 206
4.3.1 Local Memory Map .............................................................................................. 206
4.3.2 Global Memory Map............................................................................................. 207
4.4 Functional Description.................................................................................................... 208
4.4.1 PRU Cores........................................................................................................ 208
4.4.2 Interrupt Controller (INTC)...................................................................................... 225
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4.4.3 Industrial Ethernet Peripheral (IEP) ........................................................................... 233
4.4.4 Universal Asynchronous Receiver/Transmitter (UART) .................................................... 241
4.4.5 ECAP .............................................................................................................. 254
4.4.6 MII_RT ............................................................................................................ 254
4.4.7 MDIO .............................................................................................................. 272
4.5 Registers................................................................................................................... 273
4.5.1 PRU_ICSS_PRU_CTRL Registers............................................................................ 273
4.5.2 PRU_ICSS_PRU_DEBUG Registers ......................................................................... 283
4.5.3 PRU_ICSS_INTC Registers.................................................................................... 348
4.5.4 PRU_ICSS_IEP Registers...................................................................................... 412
4.5.5 PRU_ICSS_UART Registers................................................................................... 464
4.5.6 PRU_ICSS_ECAP Registers................................................................................... 483
4.5.7 PRU_ICSS_MII_RT Registers ................................................................................. 483
4.5.8 PRU_ICSS_MDIO Registers ................................................................................... 503
4.5.9 PRU_ICSS_CFG Registers .................................................................................... 503
5 Graphics Accelerator (SGX) ............................................................................................... 522
5.0.10 POWERVR SGX Main Features.............................................................................. 523
5.0.11 SGX 3D Features............................................................................................... 524
5.0.12 Universal Scalable Shader Engine (USSE) – Key Features .............................................. 525
5.0.13 Unsupported Features ......................................................................................... 525
5.1 Integration.................................................................................................................. 526
5.1.1 SGX530 Connectivity Attributes ............................................................................... 526
5.1.2 SGX530 Clock and Reset Management...................................................................... 526
5.1.3 SGX530 Pin List ................................................................................................. 527
5.2 Functional Description.................................................................................................... 528
5.2.1 SGX Block Diagram ............................................................................................. 528
5.2.2 SGX Elements Description ..................................................................................... 528
6 Interrupts......................................................................................................................... 530
6.1 Functional Description.................................................................................................... 531
6.1.1 Interrupt Processing ............................................................................................ 532
6.1.2 Register Protection .............................................................................................. 533
6.1.3 Module Power Saving........................................................................................... 533
6.1.4 Error Handling.................................................................................................... 533
6.1.5 Interrupt Handling................................................................................................ 533
6.2 Basic Programming Model............................................................................................... 534
6.2.1 Initialization Sequence .......................................................................................... 534
6.2.2 INTC Processing Sequence.................................................................................... 534
6.2.3 INTC Preemptive Processing Sequence ..................................................................... 538
6.2.4 Interrupt Preemption............................................................................................. 542
6.2.5 ARM A8 INTC Spurious Interrupt Handling .................................................................. 542
6.3 ARM Cortex-A8 Interrupts ............................................................................................... 543
6.4 Crypto DMA Events ...................................................................................................... 547
6.5 PWM Events............................................................................................................... 549
6.6 Interrupt Controller Registers............................................................................................ 550
6.6.1 INTC Registers................................................................................................... 550
7 Memory Subsystem .......................................................................................................... 596
7.1 GPMC ...................................................................................................................... 597
7.1.1 Introduction ....................................................................................................... 597
7.1.2 Integration......................................................................................................... 600
7.1.3 GPMC High-Level Programming Model Overview .......................................................... 681
7.1.4 Use Cases ........................................................................................................ 692
7.1.5 GPMC Registers ................................................................................................. 702
7.2 OCMC-RAM ............................................................................................................... 900
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7.2.1 Introduction ....................................................................................................... 900
7.2.2 Integration......................................................................................................... 901
7.3 EMIF........................................................................................................................ 902
7.3.1 Introduction ....................................................................................................... 902
7.3.2 Integration......................................................................................................... 904
7.3.3 Functional Description........................................................................................... 906
7.3.4 Use Cases ........................................................................................................ 928
7.3.5 EMIF4D Registers ............................................................................................... 928
7.3.6 DDR2/3/mDDR PHY Registers ................................................................................ 972
7.4 ELM......................................................................................................................... 982
7.4.1 Introduction ....................................................................................................... 982
7.4.2 Integration......................................................................................................... 983
7.4.3 Functional Description........................................................................................... 984
7.4.4 Basic Programming Model...................................................................................... 987
7.4.5 ELM Registers.................................................................................................... 992
8 Power, Reset, and Clock Management (PRCM) ................................................................... 1197
8.1 Power, Reset, and Clock Management .............................................................................. 1198
8.1.1 Introduction ..................................................................................................... 1198
8.1.2 Device Power-Management Architecture Building Blocks ............................................... 1198
8.1.3 Clock Management ............................................................................................ 1198
8.1.4 Power Management ........................................................................................... 1204
8.1.5 PRCM Module Overview ..................................................................................... 1215
8.1.6 Clock Generation and Management ......................................................................... 1217
8.1.7 Reset Management ............................................................................................ 1234
8.1.8 Power-Up/Down Sequence ................................................................................... 1245
8.1.9 IO State.......................................................................................................... 1246
8.1.10 Voltage and Power Domains ................................................................................ 1246
8.1.11 Device Modules and Power Management Attributes List ............................................... 1247
8.1.12 Clock Module Registers ...................................................................................... 1250
8.1.13 Power Management Registers .............................................................................. 1404
9 Control Module............................................................................................................... 1445
9.1 Introduction............................................................................................................... 1446
9.2 Functional Description .................................................................................................. 1446
9.2.1 Control Module Initialization................................................................................... 1446
9.2.2 Pad Control Registers ......................................................................................... 1446
9.2.3 EDMA Event Multiplexing ..................................................................................... 1448
9.2.4 Device Control and Status .................................................................................... 1448
9.2.5 DDR PHY........................................................................................................ 1454
9.3 Registers ................................................................................................................. 1455
9.3.1 CONTROL_MODULE Registers ............................................................................. 1455
10 Interconnects ................................................................................................................. 1558
10.1 Introduction............................................................................................................... 1559
10.1.1 Terminology.................................................................................................... 1559
10.1.2 L3 Interconnect ................................................................................................ 1559
10.1.3 L4 Interconnect ................................................................................................ 1562
11 Enhanced Direct Memory Access (EDMA).......................................................................... 1563
11.1 Introduction............................................................................................................... 1564
11.1.1 EDMA3 Controller Block Diagram .......................................................................... 1564
11.1.2 Third-Party Channel Controller (TPCC) Overview ........................................................ 1565
11.1.3 Third-Party Transfer Controller (TPTC) Overview ........................................................ 1567
11.2 Integration ................................................................................................................ 1568
11.2.1 Third-Party Channel Controller (TPCC) Integration ...................................................... 1568
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11.2.2 Third-Party Transfer Controller (TPTC) Integration....................................................... 1569
11.3 Functional Description .................................................................................................. 1571
11.3.1 Functional Overview .......................................................................................... 1571
11.3.2 Types of EDMA3 Transfers .................................................................................. 1574
11.3.3 Parameter RAM (PaRAM) ................................................................................... 1576
11.3.4 Initiating a DMA Transfer..................................................................................... 1588
11.3.5 Completion of a DMA Transfer .............................................................................. 1591
11.3.6 Event, Channel, and PaRAM Mapping..................................................................... 1592
11.3.7 EDMA3 Channel Controller Regions ....................................................................... 1594
11.3.8 Chaining EDMA3 Channels.................................................................................. 1596
11.3.9 EDMA3 Interrupts ............................................................................................. 1597
11.3.10 Memory Protection .......................................................................................... 1603
11.3.11 Event Queues ................................................................................................ 1607
11.3.12 EDMA3 Transfer Controller (EDMA3TC) ................................................................. 1609
11.3.13 Event Dataflow ............................................................................................... 1612
11.3.14 EDMA3 Prioritization ........................................................................................ 1612
11.3.15 EDMA3 Operating Frequency (Clock Control)........................................................... 1613
11.3.16 Reset Considerations ....................................................................................... 1613
11.3.17 Power Management ......................................................................................... 1613
11.3.18 Emulation Considerations .................................................................................. 1613
11.3.19 EDMA Events ................................................................................................ 1631
11.4 EDMA3 Registers ....................................................................................................... 1634
11.4.1 EDMA3CC Registers ......................................................................................... 1634
11.4.2 EDMA3TC Registers.......................................................................................... 1769
11.5 Appendix A............................................................................................................... 1822
11.5.1 Debug Checklist ............................................................................................... 1822
11.5.2 Miscellaneous Programming/Debug Tips .................................................................. 1823
11.5.3 Setting Up a Transfer......................................................................................... 1825
12 Touchscreen Controller ................................................................................................... 1827
12.1 Introduction............................................................................................................... 1828
12.1.1 TSC_ADC Features........................................................................................... 1828
12.1.2 Unsupported TSC_ADC_SS Features ..................................................................... 1828
12.2 Integration ................................................................................................................ 1829
12.2.1 TSC_ADC Connectivity Attributes .......................................................................... 1829
12.2.2 TSC_ADC Clock and Reset Management................................................................. 1830
12.2.3 TSC_ADC Pin List ............................................................................................ 1830
12.3 Functional Description .................................................................................................. 1831
12.3.1 Hardware-Synchronized or Software-Enabled ............................................................ 1831
12.3.2 Open Delay and Sample Delay ............................................................................. 1831
12.3.3 Averaging of Samples (1, 2, 4, 8, and 16) ................................................................. 1831
12.3.4 One-Shot (Single) or Continuous Mode ................................................................... 1831
12.3.5 Interrupts ....................................................................................................... 1831
12.3.6 DMA Requests ................................................................................................ 1832
12.3.7 Analog Front End (AFE) Functional Block Diagram ..................................................... 1832
12.4 Operational Modes...................................................................................................... 1834
12.4.1 PenCtrl and PenIRQ .......................................................................................... 1835
12.5 Touchscreen Controller Registers .................................................................................... 1838
12.5.1 TSC_ADC_SS Registers..................................................................................... 1838
13 LCD Controller................................................................................................................ 1920
13.1 Introduction............................................................................................................... 1921
13.1.1 Purpose of the Peripheral .................................................................................... 1921
13.1.2 Features ........................................................................................................ 1922
13.2 Integration ................................................................................................................ 1923
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