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AM335x and AMIC110 Sitara™ Processors
Technical Reference Manual
Literature Number: SPRUH73Q
October 2011–Revised December 2019
2
SPRUH73Q–October 2011–Revised December 2019
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Copyright © 2011–2019, Texas Instruments Incorporated
Contents
Contents
Preface..................................................................................................................................... 173
1 Introduction ..................................................................................................................... 174
1.1 AM335x Family............................................................................................................ 174
1.1.1 Device Features.................................................................................................. 174
1.1.2 Device Identification ............................................................................................. 174
1.2 Silicon Revision Functional Differences and Enhancements ....................................................... 174
1.2.1 Added RTC Alarm Wakeup for DeepSleep Modes.......................................................... 174
1.2.2 Changed BOOTP Identifier..................................................................................... 174
1.2.3 Changed Product String in USB Descriptor .................................................................. 175
1.2.4 Added DPLL Power Switch Control and Status Registers ................................................. 175
1.2.5 Added Control for CORE SRAM LDO Retention Mode..................................................... 175
1.2.6 Added Pin Mux Options for GPMC_A9 to Facilitate RMII Pin Muxing.................................... 175
1.2.7 Changed Polarity of Input Signal nNMI (Pin EXTINTn)..................................................... 175
1.2.8 Changed Default Value of ncin and pcin Bits in vtp_ctrl Register......................................... 176
1.2.9 Changed Default Value of RGMII Mode to No Internal Delay ............................................. 176
1.2.10 Changed Default Value of RMII Clock Source.............................................................. 176
1.2.11 Changed the Method of Determining Speed of Operation During EMAC Boot ........................ 176
1.2.12 Added EFUSE_SMA Register for Help Identifying Different Device Variants .......................... 176
2 Memory Map .................................................................................................................... 177
2.1 ARM Cortex-A8 Memory Map........................................................................................... 177
3 ARM MPU Subsystem ....................................................................................................... 186
3.1 ARM Cortex-A8 MPU Subsystem ...................................................................................... 187
3.1.1 Features........................................................................................................... 188
3.1.2 MPU Subsystem Integration.................................................................................... 188
3.1.3 MPU Subsystem Clock and Reset Distribution .............................................................. 189
3.1.4 ARM Subchip..................................................................................................... 192
3.1.5 Interrupt Controller............................................................................................... 193
3.1.6 Power Management ............................................................................................. 194
3.1.7 ARM Programming Model ...................................................................................... 196
4 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-
ICSS)............................................................................................................................... 198
4.1 Introduction ................................................................................................................ 199
4.1.1 Features........................................................................................................... 200
4.2 Integration.................................................................................................................. 201
4.2.1 PRU-ICSS Connectivity Attributes............................................................................. 202
4.2.2 PRU-ICSS Clock and Reset Management ................................................................... 202
4.2.3 PRU-ICSS Pin List............................................................................................... 203
4.2.4 PRU-ICSS Internal Pinmux..................................................................................... 204
4.3 PRU-ICSS Memory Map Overview..................................................................................... 206
4.3.1 Local Memory Map .............................................................................................. 206
4.3.2 Global Memory Map............................................................................................. 207
4.4 Functional Description.................................................................................................... 208
4.4.1 PRU Cores........................................................................................................ 208
4.4.2 Interrupt Controller (INTC)...................................................................................... 225
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Contents
4.4.3 Industrial Ethernet Peripheral (IEP) ........................................................................... 233
4.4.4 Universal Asynchronous Receiver/Transmitter (UART) .................................................... 241
4.4.5 ECAP .............................................................................................................. 254
4.4.6 MII_RT ............................................................................................................ 254
4.4.7 MDIO .............................................................................................................. 273
4.5 Registers................................................................................................................... 274
4.5.1 PRU_ICSS_PRU_CTRL Registers............................................................................ 274
4.5.2 PRU_ICSS_PRU_DEBUG Registers ......................................................................... 284
4.5.3 PRU_ICSS_INTC Registers.................................................................................... 349
4.5.4 PRU_ICSS_IEP Registers...................................................................................... 413
4.5.5 PRU_ICSS_UART Registers................................................................................... 464
4.5.6 PRU_ICSS_ECAP Registers................................................................................... 483
4.5.7 PRU_ICSS_MII_RT Registers ................................................................................. 483
4.5.8 PRU_ICSS_MDIO Registers ................................................................................... 503
4.5.9 PRU_ICSS_CFG Registers .................................................................................... 503
5 Graphics Accelerator (SGX) ............................................................................................... 522
5.0.10 POWERVR SGX Main Features.............................................................................. 523
5.0.11 SGX 3D Features............................................................................................... 524
5.0.12 Universal Scalable Shader Engine (USSE) – Key Features .............................................. 525
5.0.13 Unsupported Features ......................................................................................... 525
5.1 Integration.................................................................................................................. 526
5.1.1 SGX530 Connectivity Attributes ............................................................................... 526
5.1.2 SGX530 Clock and Reset Management...................................................................... 526
5.1.3 SGX530 Pin List ................................................................................................. 527
5.2 Functional Description.................................................................................................... 528
5.2.1 SGX Block Diagram ............................................................................................. 528
5.2.2 SGX Elements Description ..................................................................................... 528
6 Interrupts......................................................................................................................... 530
6.1 Functional Description.................................................................................................... 531
6.1.1 Interrupt Processing ............................................................................................ 532
6.1.2 Register Protection .............................................................................................. 533
6.1.3 Module Power Saving........................................................................................... 533
6.1.4 Error Handling.................................................................................................... 533
6.1.5 Interrupt Handling................................................................................................ 533
6.2 Basic Programming Model............................................................................................... 534
6.2.1 Initialization Sequence .......................................................................................... 534
6.2.2 INTC Processing Sequence.................................................................................... 534
6.2.3 INTC Preemptive Processing Sequence ..................................................................... 538
6.2.4 Interrupt Preemption............................................................................................. 542
6.2.5 ARM A8 INTC Spurious Interrupt Handling .................................................................. 542
6.3 ARM Cortex-A8 Interrupts ............................................................................................... 543
6.4 Crypto DMA Events ...................................................................................................... 547
6.5 PWM Events............................................................................................................... 549
6.6 Interrupt Controller Registers............................................................................................ 550
6.6.1 INTC Registers................................................................................................... 550
7 Memory Subsystem .......................................................................................................... 596
7.1 GPMC ...................................................................................................................... 597
7.1.1 Introduction ....................................................................................................... 597
7.1.2 Integration......................................................................................................... 600
7.1.3 GPMC High-Level Programming Model Overview .......................................................... 681
7.1.4 Use Cases ........................................................................................................ 692
7.1.5 GPMC Registers ................................................................................................. 702
7.2 OCMC-RAM ............................................................................................................... 900
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Contents
7.2.1 Introduction ....................................................................................................... 900
7.2.2 Integration......................................................................................................... 901
7.3 EMIF........................................................................................................................ 902
7.3.1 Introduction ....................................................................................................... 902
7.3.2 Integration......................................................................................................... 904
7.3.3 Functional Description........................................................................................... 906
7.3.4 Use Cases ........................................................................................................ 928
7.3.5 EMIF4D Registers ............................................................................................... 928
7.3.6 DDR2/3/mDDR PHY Registers ................................................................................ 972
7.4 ELM......................................................................................................................... 982
7.4.1 Introduction ....................................................................................................... 982
7.4.2 Integration......................................................................................................... 983
7.4.3 Functional Description........................................................................................... 984
7.4.4 Basic Programming Model...................................................................................... 987
7.4.5 ELM Registers.................................................................................................... 992
8 Power, Reset, and Clock Management (PRCM) ................................................................... 1197
8.1 Power, Reset, and Clock Management .............................................................................. 1198
8.1.1 Introduction ..................................................................................................... 1198
8.1.2 Device Power-Management Architecture Building Blocks ............................................... 1198
8.1.3 Clock Management ............................................................................................ 1198
8.1.4 Power Management ........................................................................................... 1204
8.1.5 PRCM Module Overview ..................................................................................... 1215
8.1.6 Clock Generation and Management ......................................................................... 1217
8.1.7 Reset Management ............................................................................................ 1237
8.1.8 Power-Up/Down Sequence ................................................................................... 1248
8.1.9 IO State.......................................................................................................... 1249
8.1.10 Voltage and Power Domains ................................................................................ 1249
8.1.11 Device Modules and Power Management Attributes List ............................................... 1250
8.1.12 Clock Module Registers ...................................................................................... 1253
8.1.13 Power Management Registers .............................................................................. 1407
9 Control Module............................................................................................................... 1448
9.1 Introduction............................................................................................................... 1449
9.2 Functional Description .................................................................................................. 1449
9.2.1 Control Module Initialization................................................................................... 1449
9.2.2 Pad Control Registers ......................................................................................... 1449
9.2.3 EDMA Event Multiplexing ..................................................................................... 1451
9.2.4 Device Control and Status .................................................................................... 1451
9.2.5 DDR PHY........................................................................................................ 1457
9.3 Registers ................................................................................................................. 1458
9.3.1 CONTROL_MODULE Registers ............................................................................. 1458
10 Interconnects ................................................................................................................. 1561
10.1 Introduction............................................................................................................... 1562
10.1.1 Terminology.................................................................................................... 1562
10.1.2 L3 Interconnect ................................................................................................ 1562
10.1.3 L4 Interconnect ................................................................................................ 1565
11 Enhanced Direct Memory Access (EDMA).......................................................................... 1566
11.1 Introduction............................................................................................................... 1567
11.1.1 EDMA3 Controller Block Diagram .......................................................................... 1567
11.1.2 Third-Party Channel Controller (TPCC) Overview ........................................................ 1568
11.1.3 Third-Party Transfer Controller (TPTC) Overview ........................................................ 1570
11.2 Integration ................................................................................................................ 1571
11.2.1 Third-Party Channel Controller (TPCC) Integration ...................................................... 1571
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Contents
11.2.2 Third-Party Transfer Controller (TPTC) Integration....................................................... 1572
11.3 Functional Description .................................................................................................. 1574
11.3.1 Functional Overview .......................................................................................... 1574
11.3.2 Types of EDMA3 Transfers .................................................................................. 1577
11.3.3 Parameter RAM (PaRAM) ................................................................................... 1579
11.3.4 Initiating a DMA Transfer..................................................................................... 1591
11.3.5 Completion of a DMA Transfer .............................................................................. 1594
11.3.6 Event, Channel, and PaRAM Mapping..................................................................... 1595
11.3.7 EDMA3 Channel Controller Regions ....................................................................... 1597
11.3.8 Chaining EDMA3 Channels.................................................................................. 1600
11.3.9 EDMA3 Interrupts ............................................................................................. 1600
11.3.10 Memory Protection .......................................................................................... 1607
11.3.11 Event Queues ................................................................................................ 1611
11.3.12 EDMA3 Transfer Controller (EDMA3TC) ................................................................. 1613
11.3.13 Event Dataflow ............................................................................................... 1616
11.3.14 EDMA3 Prioritization ........................................................................................ 1616
11.3.15 EDMA3 Operating Frequency (Clock Control)........................................................... 1617
11.3.16 Reset Considerations ....................................................................................... 1617
11.3.17 Power Management ......................................................................................... 1617
11.3.18 Emulation Considerations .................................................................................. 1617
11.3.19 EDMA Transfer Examples .................................................................................. 1619
11.3.20 EDMA Events ................................................................................................ 1635
11.4 EDMA3 Registers ....................................................................................................... 1638
11.4.1 EDMA3CC Registers ......................................................................................... 1638
11.4.2 EDMA3TC Registers.......................................................................................... 1773
11.5 Appendix A............................................................................................................... 1826
11.5.1 Debug Checklist ............................................................................................... 1826
11.5.2 Miscellaneous Programming/Debug Tips .................................................................. 1827
11.5.3 Setting Up a Transfer......................................................................................... 1829
12 Touchscreen Controller ................................................................................................... 1831
12.1 Introduction............................................................................................................... 1832
12.1.1 TSC_ADC Features........................................................................................... 1832
12.1.2 Unsupported TSC_ADC_SS Features ..................................................................... 1832
12.2 Integration ................................................................................................................ 1833
12.2.1 TSC_ADC Connectivity Attributes .......................................................................... 1833
12.2.2 TSC_ADC Clock and Reset Management................................................................. 1834
12.2.3 TSC_ADC Pin List ............................................................................................ 1834
12.3 Functional Description .................................................................................................. 1835
12.3.1 Hardware-Synchronized or Software-Enabled ............................................................ 1835
12.3.2 Open Delay and Sample Delay ............................................................................. 1835
12.3.3 Averaging of Samples (1, 2, 4, 8, and 16) ................................................................. 1835
12.3.4 One-Shot (Single) or Continuous Mode ................................................................... 1835
12.3.5 Interrupts ....................................................................................................... 1835
12.3.6 DMA Requests ................................................................................................ 1836
12.3.7 Analog Front End (AFE) Functional Block Diagram ..................................................... 1836
12.4 Operational Modes...................................................................................................... 1838
12.4.1 PenCtrl and PenIRQ .......................................................................................... 1839
12.5 Touchscreen Controller Registers .................................................................................... 1842
12.5.1 TSC_ADC_SS Registers..................................................................................... 1842
13 LCD Controller................................................................................................................ 1924
13.1 Introduction............................................................................................................... 1925
13.1.1 Purpose of the Peripheral .................................................................................... 1925
13.1.2 Features ........................................................................................................ 1926
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