PCI Express
®
Base Specification
Revision 3.0
November 10, 2010
2
Revision Revision History DATE
1.0 Initial release. 07/22/2002
1.0a Incorporated Errata C1-C66 and E1-E4.17. 04/15/2003
1.1 Incorporated approved Errata and ECNs. 03/28/2005
2.0 Added 5.0 GT/s data rate and incorporated approved Errata and ECNs. 12/20/2006
2.1 Incorporated Errata for the PCI Express Base Specification, Rev. 2.0
(February 27, 2009), and added the following ECNs:
• Internal Error Reporting ECN (April 24, 2008)
• Multicast ECN (December 14, 2007, approved by PWG May 8, 2008)
• Atomic Operations ECN (January 15, 2008, approved by PWG April 17, 2008)
• Resizable BAR Capability ECN (January 22, 2008, updated and approved by
PWG April 24, 2008)
• Dynamic Power Allocation ECN (May 24, 2008)
• ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008)
• Latency Tolerance Reporting ECN (22 January 2008, updated 14 August 2008)
• Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last updated
June 4, 2007)
• Extended Tag Enable Default ECN (September 5, 2008)
• TLP Processing Hints ECN (September 11, 2008)
• TLP Prefix ECN (December 15, 2008)
03/04/2009
3.0 Added 8.0 GT/s data rate, latest approved Errata, and the following ECNs:
• Optimized Buffer Flush/Fill ECN (8 February 2008, updated 30 April 2009)
• ASPM Optionality ECN (June 19, 2009, approved by the PWG August 20, 2009)
• Incorporated End-End TLP Changes for RCs ECN (26 May 2010) and Protocol
Multiplexing ECN (17 June 2010)
11/10/2010
PCI-SIG
®
disclaims all warranties and liability for the use of this document and the information contained herein and
assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to
update the information contained herein.
Contact the PCI-SIG office to obtain the latest revision of this specification.
Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be forwarded to:
Membership Services
www.pcisig.com
E-mail: administration@pcisig.com
Phone: 503-619-0569
Fax: 503-644-6708
Technical Support
techsupp@pcisig.com
DISCLAIMER
This PCI Express Base Specification is provided “as is” with no warranties whatsoever, including any warranty of
merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any
proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to
use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted herein.
PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG.
All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.
Copyright © 2002-2010 PCI-SIG
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
3
Contents
OBJECTIVE OF THE SPECIFICATION.................................................................................... 27
DOCUMENT ORGANIZATION ................................................................................................ 27
DOCUMENTATION CONVENTIONS...................................................................................... 28
TERMS AND ACRONYMS........................................................................................................ 29
REFERENCE DOCUMENTS...................................................................................................... 36
1. INTRODUCTION ................................................................................................................ 37
1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 37
1.2. PCI EXPRESS LINK......................................................................................................... 39
1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 41
1.3.1. Root Complex........................................................................................................ 41
1.3.2. Endpoints .............................................................................................................. 42
1.3.3. Switch.................................................................................................................... 45
1.3.4. Root Complex Event Collector.............................................................................. 46
1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 46
1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION....................................................... 46
1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 47
1.5.1. Transaction Layer................................................................................................. 48
1.5.2. Data Link Layer.................................................................................................... 48
1.5.3. Physical Layer ...................................................................................................... 49
1.5.4. Layer Functions and Services............................................................................... 49
2. TRANSACTION LAYER SPECIFICATION ..................................................................... 53
2.1. T
RANSACTION LAYER OVERVIEW.................................................................................. 53
2.1.1. Address Spaces, Transaction Types, and Usage................................................... 54
2.1.2. Packet Format Overview ...................................................................................... 56
2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 58
2.2.1. Common Packet Header Fields ............................................................................ 58
2.2.2. TLPs with Data Payloads - Rules......................................................................... 61
2.2.3. TLP Digest Rules .................................................................................................. 65
2.2.4. Routing and Addressing Rules.............................................................................. 65
2.2.5. First/Last DW Byte Enables Rules........................................................................ 69
2.2.6. Transaction Descriptor......................................................................................... 71
2.2.7. Memory, I/O, and Configuration Request Rules................................................... 77
2.2.8. Message Request Rules......................................................................................... 83
2.2.9. Completion Rules.................................................................................................. 97
2.2.10. TLP Prefix Rules................................................................................................. 100
2.3. H
ANDLING OF RECEIVED TLPS.................................................................................... 104
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
4
2.3.1. Request Handling Rules...................................................................................... 107
2.3.2. Completion Handling Rules................................................................................ 120
2.4. TRANSACTION ORDERING............................................................................................ 122
2.4.1. Transaction Ordering Rules ............................................................................... 122
2.4.2. Update Ordering and Granularity Observed by a Read Transaction................ 126
2.4.3. Update Ordering and Granularity Provided by a Write Transaction................ 127
2.5. VIRTUAL CHANNEL (VC) MECHANISM........................................................................ 128
2.5.1. Virtual Channel Identification (VC ID).............................................................. 130
2.5.2. TC to VC Mapping.............................................................................................. 131
2.5.3. VC and TC Rules................................................................................................. 132
2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 133
2.6.1. Flow Control Rules............................................................................................. 134
2.7. DATA INTEGRITY ......................................................................................................... 145
2.7.1. ECRC Rules ........................................................................................................ 145
2.7.2. Error Forwarding............................................................................................... 149
2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 151
2.9. LINK STATUS DEPENDENCIES ...................................................................................... 151
2.9.1. Transaction Layer Behavior in DL_Down Status............................................... 151
2.9.2. Transaction Layer Behavior in DL_Up Status ................................................... 153
3. DATA LINK LAYER SPECIFICATION.......................................................................... 155
3.1. DATA LINK LAYER OVERVIEW .................................................................................... 155
3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 157
3.2.1. Data Link Control and Management State Machine Rules ................................ 158
3.3. FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 160
3.3.1. Flow Control Initialization State Machine Rules ............................................... 160
3.4. DATA LINK LAYER PACKETS (DLLPS)........................................................................ 164
3.4.1. Data Link Layer Packet Rules ............................................................................ 164
3.5. DATA INTEGRITY ......................................................................................................... 169
3.5.1. Introduction......................................................................................................... 169
3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 169
3.5.3. LCRC and Sequence Number (TLP Receiver).................................................... 182
4. PHYSICAL LAYER SPECIFICATION............................................................................ 191
4.1. I
NTRODUCTION ............................................................................................................ 191
4.2. LOGICAL SUB-BLOCK................................................................................................... 191
4.2.1. Encoding for 2.5 GT/s and 5.0 GT/s Data Rates................................................ 192
4.2.2. Encoding for 8.0 GT/s and Higher Data Rates................................................... 200
4.2.3. Link Equalization Procedure for 8.0 GT/s Data Rate ........................................ 218
4.2.4. Link Initialization and Training.......................................................................... 226
4.2.5. Link Training and Status State Machine (LTSSM) Descriptions........................ 244
4.2.6. Link Training and Status State Rules.................................................................. 247
4.2.7. Clock Tolerance Compensation.......................................................................... 314
4.2.8. Compliance Pattern in 8b/10b Encoding............................................................ 317
4.2.9. Modified Compliance Pattern in 8b/10b Encoding ............................................ 318
4.2.10. Compliance Pattern in 128b/130b Encoding...................................................... 320
4.2.11. Modified Compliance Pattern in 128b/130b Encoding ...................................... 322
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
5
4.3. ELECTRICAL SUB-BLOCK ............................................................................................. 323
4.3.1. Electrical Specification Organization................................................................. 323
4.3.2. Interoperability Criteria for 2.5, 5.0, and 8.0 GT/s Devices .............................. 323
4.3.3. Transmitter Specification.................................................................................... 325
4.3.4. Receiver Specifications....................................................................................... 359
4.3.5. Low Frequency and Miscellaneous Signaling Requirements............................. 382
4.3.6. Channel Specification......................................................................................... 387
4.3.7. Refclk Specifications........................................................................................... 400
4.3.8. Refclk Specifications for 8.0 GT/s....................................................................... 408
5. POWER MANAGEMENT................................................................................................. 413
5.1. OVERVIEW ................................................................................................................... 413
5.1.1. Statement of Requirements.................................................................................. 414
5.2. LINK STATE POWER MANAGEMENT............................................................................. 414
5.3. PCI-PM
SOFTWARE COMPATIBLE MECHANISMS......................................................... 419
5.3.1. Device Power Management States (D-States) of a Function.............................. 419
5.3.2. PM Software Control of the Link Power Management State.............................. 424
5.3.3. Power Management Event Mechanisms............................................................. 429
5.4. N
ATIVE PCI EXPRESS POWER MANAGEMENT MECHANISMS....................................... 436
5.4.1. Active State Power Management (ASPM) .......................................................... 436
5.5. AUXILIARY POWER SUPPORT....................................................................................... 455
5.5.1. Auxiliary Power Enabling................................................................................... 455
5.6. POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS............................................. 456
6. SYSTEM ARCHITECTURE ............................................................................................. 459
6.1. INTERRUPT AND PME SUPPORT ................................................................................... 459
6.1.1. Rationale for PCI Express Interrupt Model........................................................ 459
6.1.2. PCI Compatible INTx Emulation........................................................................ 460
6.1.3. INTx Emulation Software Model ........................................................................ 460
6.1.4. Message Signaled Interrupt (MSI/MSI-X) Support............................................. 460
6.1.5. PME Support....................................................................................................... 462
6.1.6. Native PME Software Model .............................................................................. 462
6.1.7. Legacy PME Software Model ............................................................................. 463
6.1.8. Operating System Power Management Notification........................................... 463
6.1.9. PME Routing Between PCI Express and PCI Hierarchies ................................ 463
6.2. E
RROR SIGNALING AND LOGGING................................................................................ 464
6.2.1. Scope................................................................................................................... 464
6.2.2. Error Classification............................................................................................ 464
6.2.3. Error Signaling................................................................................................... 466
6.2.4. Error Logging..................................................................................................... 474
6.2.5. Sequence of Device Error Signaling and Logging Operations .......................... 478
6.2.6. Error Message Controls ..................................................................................... 480
6.2.7. Error Listing and Rules ...................................................................................... 481
6.2.8. Virtual PCI Bridge Error Handling.................................................................... 486
6.2.9. Internal Errors.................................................................................................... 488
6.3. VIRTUAL CHANNEL SUPPORT ...................................................................................... 489
6.3.1. Introduction and Scope....................................................................................... 489
评论0