基于FPGA的PWM信号发生器代码+仿真

Debug for fit_fastio_pin_reassign program (iteration 1): I/O delay matrix:- Comb Reg SU Pin Cout Casc Clk N/A 45 N/A 51 N/A N/A Clr N/A 45 N/A 51 N/A N/A Pre N/A 41 N/A 47 N/A N/A Ena N/A N/A 19 N/A N/A N/A Ald N/A 41 N/A 47 N/A N/A OE N/A N/A N/A 48 N/A N/A Cin N/A N/A N/A N/A N/A N/A Casc N/A N/A N/A N/A N/A N/A Pin 24 N/A 93 N/A N/A N/A A N/A N/A 14 30 N/A N/A B N/A N/A N/A N/A N/A N/A C N/A N/A N/A N/A N/A N/A D N/A N/A N/A N/A N/A N/A Global clock delay matrix:- Comb Reg SU Pin Cout Casc Clk : N/A 5 24 N/A 12 N/A Clr : N/A 12 N/A N/A 19 N/A Pre : N/A 12 N/A N/A 19 N/A Ena : N/A N/A 16 N/A N/A N/A Ald : N/A 12 N/A N/A 19 N/A OE : N/A N/A N/A N/A N/A N/A Cin : 14 N/A 14 N/A 2 18 Casc: 6 N/A 6 N/A N/A 10 Pin : N/A N/A N/A N/A N/A N/A A : 17 N/A 17 N/A 7 21 B : 16 N/A 16 N/A 7 20 C : 16 N/A 16 N/A N/A 20 D : 14 N/A 14 N/A N/A 18 I/O delay matrix:- Comb Reg SU Pin Cout Casc Clk N/A 45 N/A 51 N/A N/A Clr N/A 45 N/A 51 N/A N/A Pre N/A 41 N/A 47 N/A N/A Ena N/A N/A 19 N/A N/A N/A Ald N/A 41 N/A 47 N/A N/A OE N/A N/A N/A 48 N/A N/A Cin N/A N/A N/A N/A N/A N/A Casc N/A N/A N/A N/A N/A N/A Pin 24 N/A 93 N/A N/A N/A A N/A N/A 14 30 N/A N/A B N/A N/A N/A N/A N/A N/A C N/A N/A N/A N/A N/A N/A D N/A N/A N/A N/A N/A N/A Global clock delay matrix:- Comb Reg SU Pin Cout Casc Clk : N/A 5 24 N/A 12 N/A Clr : N/A 12 N/A N/A 19 N/A Pre : N/A 12 N/A N/A 19 N/A Ena : N/A N/A 16 N/A N/A N/A Ald : N/A 12 N/A N/A 19 N/A OE : N/A N/A N/A N/A N/A N/A Cin : 14 N/A 14 N/A 2 18 Casc: 6 N/A 6 N/A N/A 10 Pin : N/A N/A N/A N/A N/A N/A A : 17 N/A 17 N/A 7 21 B : 16 N/A 16 N/A 7 20 C : 16 N/A 16 N/A N/A 20 D : 14 N/A 14 N/A N/A 18 Threshold are: for Tsu - 8.200000ns and for Tco - 14.600000ns Global Tsu=-1(-1.000000), Tco=-1(-1.000000) Input/output cells: ADDA -> 73 : OUT ALE -> 78 : OUT CLK -> 124 : IN D0 -> 30 : IN D1 -> 31 : IN D2 -> 32 : IN D3 -> 33 : IN D4 -> 36 : IN D5 -> 37 : IN D6 -> 38 : IN D7 -> 39 : IN EOC -> 20 : IN OE -> 80 : OUT P10 -> 119 : OUT P11 -> 118 : OUT P12 -> 117 : OUT P13 -> 116 : OUT P14 -> 114 : OUT P15 -> 113 : OUT P16 -> 112 : OUT P17 -> 111 : OUT P32 -> 110 : OUT P33 -> 109 : OUT P34 -> 11 : OUT P35 -> 14 : OUT P36 -> 7 : OUT P37 -> 144 : OUT Q0 -> 87 : OUT Q1 -> 88 : OUT Q2 -> 89 : OUT Q3 -> 90 : OUT Q4 -> 91 : OUT Q5 -> 92 : OUT Q6 -> 95 : OUT Q7 -> 96 : OUT START -> 79 : OUT Set clique dont_touch: Cell: ADDA, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: ALE, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: CLK, rdfbits: d, fast_io bit: 0, periphery: 0,0 Cell: D0, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: D1, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: D2, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: D3, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: D4, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: D5, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: D6, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: D7, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: EOC, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: OE, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P10, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P11, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P12, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P13, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P14, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P15, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P16, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P17, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P32, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P33, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P34, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P35, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P36, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: P37, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: Q0, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: Q1, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: Q2, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: Q3, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: Q4, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: Q5, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: Q6, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: Q7, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: START, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: :37, rdfbits: 110, fast_io bit: 0, periphery: 0,0 Cell: :38, rdfbits: 110, fast_io bit: 0, periphery: 0,0 Cell: :39, rdfbits: 110, fast_io bit: 0, periphery: 0,0 Cell: :44, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: :45, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: :46, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: :47, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: :48, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: :49, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: :50, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: :51, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: :377, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: :401, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: :425, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: :449, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Virtual pin individual set-up and clock-to-output times: For pin ADDA delays are: tsu=-1, tco=-1; For pin ALE delays are: tsu=-1, tco=-1; For pin CLK delays are: tsu=-1, tco=-1; For pin D0 delays are: tsu=-1, tco=-1; For pin D1 delays are: tsu=-1, tco=-1; For pin D2 delays are: tsu=-1, tco=-1; For pin D3 delays are: tsu=-1, tco=-1; For pin D4 delays are: tsu=-1, tco=-1; For pin D5 delays are: tsu=-1, tco=-1; For pin D6 delays are: tsu=-1, tco=-1; For pin D7 delays are: tsu=-1, tco=-1; For pin EOC delays are: tsu=-1, tco=-1; For pin OE delays are: tsu=-1, tco=-1; For pin P10 delays are: tsu=-1, tco=-1; For pin P11 delays are: tsu=-1, tco=-1; For pin P12 delays are: tsu=-1, tco=-1; For pin P13 delays are: tsu=-1, tco=-1; For pin P14 delays are: tsu=-1, tco=-1; For pin P15 delays are: tsu=-1, tco=-1; For pin P16 delays are: tsu=-1, tco=-1; For pin P17 delays are: tsu=-1, tco=-1; For pin P32 delays are: tsu=-1, tco=-1; For pin P33 delays are: tsu=-1, tco=-1; For pin P34 delays are: tsu=-1, tco=-1; For pin P35 delays are: tsu=-1, tco=-1; For pin P36 delays are: tsu=-1, tco=-1; For pin P37 delays are: tsu=-1, tco=-1; For pin Q0 delays are: tsu=-1, tco=-1; For pin Q1 delays are: tsu=-1, tco=-1; For pin Q2 delays are: tsu=-1, tco=-1; For pin Q3 delays are: tsu=-1, tco=-1; For pin Q4 delays are: tsu=-1, tco=-1; For pin Q5 delays are: tsu=-1, tco=-1; For pin Q6 delays are: tsu=-1, tco=-1; For pin Q7 delays are: tsu=-1, tco=-1; For pin START delays are: tsu=-1, tco=-1; Cells driven by pins :51 is driven by D0 :50 is driven by D1 :49 is driven by D2 :48 is driven by D3 :47 is driven by D4 :46 is driven by D5 :45 is driven by D6 :44 is driven by D7 :37 is driven by EOC :38 is driven by EOC :39 is driven by EOC Cells driving pins :377 drives ALE :425 drives OE :51 drives Q0 :50 drives Q1 :49 drives Q2 :48 drives Q3 :47 drives Q4 :46 drives Q5 :45 drives Q6 :44 drives Q7 :401 drives START FAST I/O assignement after cleaning up: ADDA: fast_io=0 ALE: fast_io=0 CLK: fast_io=0 D0: fast_io=0 D1: fast_io=0 D2: fast_io=0 D3: fast_io=0 D4: fast_io=0 D5: fast_io=0 D6: fast_io=0 D7: fast_io=0 EOC: fast_io=0 OE: fast_io=0 P10: fast_io=0 P11: fast_io=0 P12: fast_io=0 P13: fast_io=0 P14: fast_io=0 P15: fast_io=0 P16: fast_io=0 P17: fast_io=0 P32: fast_io=0 P33: fast_io=0 P34: fast_io=0 P35: fast_io=0 P36: fast_io=0 P37: fast_io=0 Q0: fast_io=0 Q1: fast_io=0 Q2: fast_io=0 Q3: fast_io=0 Q4: fast_io=0 Q5: fast_io=0 Q6: fast_io=0 Q7: fast_io=0 START: