/* Core file for MiraMEMS 3-Axis Accelerometer's driver.
*
* mir3da_core.c - Linux kernel modules for 3-Axis Accelerometer
*
* Copyright (C) 2011-2013 MiraMEMS Sensing Technology Co., Ltd.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include "mir3da_core.h"
#include "mir3da_cust.h"
#define MIR3DA_REG_ADDR(REG) ((REG)&0xFF)
#define MIR3DA_OFFSET_THRESHOLD 20
#define PEAK_LVL 800
#define STICK_LSB 2000
#define AIX_HISTORY_SIZE 20
typedef struct reg_obj_s {
short addr;
unsigned char mask;
unsigned char value;
} reg_obj_t;
struct gsensor_data_fmt_s {
unsigned char msbw;
unsigned char lsbw;
unsigned char endian; /* 0: little endian; 1: big endian */
};
struct gsensor_data_obj_s {
#define MIR3DA_DATA_LEN 6
reg_obj_t data_sect[MIR3DA_DATA_LEN];
struct gsensor_data_fmt_s data_fmt;
};
struct gsensor_obj_s {
char asic[10];
reg_obj_t chip_id;
reg_obj_t mod_id;
reg_obj_t soft_reset;
reg_obj_t power;
#define MIR3DA_INIT_SECT_LEN 11
#define MIR3DA_OFF_SECT_LEN MIR3DA_OFFSET_LEN
#define MIR3DA_ODR_SECT_LEN 3
reg_obj_t init_sect[MIR3DA_INIT_SECT_LEN];
reg_obj_t offset_sect[MIR3DA_OFF_SECT_LEN];
reg_obj_t odr_sect[MIR3DA_ODR_SECT_LEN];
struct gsensor_data_obj_s data;
int (*calibrate)(MIR_HANDLE handle, int z_dir);
int (*auto_calibrate)(MIR_HANDLE handle, int xyz[3]);
int (*int_ops)(MIR_HANDLE handle, mir_int_ops_t *ops);
int (*get_reg_data)(MIR_HANDLE handle, char *buf);
};
struct gsensor_drv_s {
struct general_op_s *method;
struct gsensor_obj_s *obj;
};
typedef enum _asic_type{
ASIC_NONE,
ASIC_2511,
ASIC_2512B,
ASIC_2513A,
ASIC_2516,
} asic_type;
typedef enum _mems_type{
MEMS_NONE,
MEMS_T4,
MEMS_T9,
MEMS_TV03,
MEMS_RTO3,
MEMS_GT2,
MEMS_GT3,
} mems_type;
typedef enum _package_type{
PACKAGE_NONE,
PACKAGE_2X2_12PIN,
PACKAGE_3X3_10PIN,
PACKAGE_3X3_16PIN,
} package_type;
struct chip_info_s{
unsigned char reg_value;
package_type package;
asic_type asic;
mems_type mems;
};
struct chip_info_s gsensor_chip_info;
static struct chip_info_s mir3da_chip_info_list[]=
{
{0x00,PACKAGE_2X2_12PIN,ASIC_2512B,MEMS_TV03},
{0x01,PACKAGE_2X2_12PIN,ASIC_2511,MEMS_T4},
{0x02,PACKAGE_2X2_12PIN,ASIC_2511,MEMS_T9},
{0x03,PACKAGE_3X3_10PIN,ASIC_2511,MEMS_T4},
{0x04,PACKAGE_3X3_10PIN,ASIC_2511,MEMS_T9},
{0x05,PACKAGE_3X3_10PIN,ASIC_2511,MEMS_T4},
{0x06,PACKAGE_3X3_10PIN,ASIC_2511,MEMS_T9},
{0x07,PACKAGE_3X3_16PIN,ASIC_2511,MEMS_T4},
{0x08,PACKAGE_3X3_16PIN,ASIC_2511,MEMS_T9},
{0x09,PACKAGE_2X2_12PIN,ASIC_2511,MEMS_T4},
{0x0c,PACKAGE_2X2_12PIN,ASIC_2512B,MEMS_T9},
{0x33,PACKAGE_2X2_12PIN,ASIC_2511,MEMS_T9},
{0x34,PACKAGE_2X2_12PIN,ASIC_2511,MEMS_T9},
{0x35,PACKAGE_2X2_12PIN,ASIC_2511,MEMS_T9},
};
#define MIR3DA_NSA_INIT_SECTION { NSA_REG_G_RANGE, 0xF3, 0x61 }, \
{ NSA_REG_POWERMODE_BW, 0xFF, 0x3e }, \
{ NSA_REG_ODR_AXIS_DISABLE, 0xFF, 0x07 }, \
{ NSA_REG_INTERRUPT_SETTINGS2, 0xFF, 0x00 }, \
{ NSA_REG_INTERRUPT_MAPPING2, 0xFF, 0x00 }, \
{ NSA_REG_ENGINEERING_MODE, 0xFF, 0x83 }, \
{ NSA_REG_ENGINEERING_MODE, 0xFF, 0x69 }, \
{ NSA_REG_ENGINEERING_MODE, 0xFF, 0xBD }, \
{ NSA_REG_INT_PIN_CONFIG, 0x0F, 0x05 }, \
{ -1, 0x00, 0x00 }, \
{ -1, 0x00, 0x00 }, \
#define MIR3DA_NSA_OFFSET_SECTION { NSA_REG_COARSE_OFFSET_TRIM_X, 0xFF, 0x00 }, \
{ NSA_REG_COARSE_OFFSET_TRIM_Y, 0xFF, 0x00 }, \
{ NSA_REG_COARSE_OFFSET_TRIM_Z, 0xFF, 0x00 }, \
{ NSA_REG_FINE_OFFSET_TRIM_X, 0xFF, 0x00 }, \
{ NSA_REG_FINE_OFFSET_TRIM_Y, 0xFF, 0x00 }, \
{ NSA_REG_FINE_OFFSET_TRIM_Z, 0xFF, 0x00 }, \
{ NSA_REG_CUSTOM_OFFSET_X, 0xFF, 0x00 }, \
{ NSA_REG_CUSTOM_OFFSET_Y, 0xFF, 0x00 }, \
{ NSA_REG_CUSTOM_OFFSET_Z, 0xFF, 0x00 }, \
#define MIR3DA_NSA_ODR_SECTION { NSA_REG_ODR_AXIS_DISABLE, 0x0F, 0x06 }, \
{ NSA_REG_ODR_AXIS_DISABLE, 0x0F, 0x07 }, \
{ NSA_REG_ODR_AXIS_DISABLE, 0x0F, 0x08 }, \
#define MIR3DA_NSA_DATA_SECTION { { NSA_REG_ACC_X_LSB, 0xFF, 0x00 }, \
{ NSA_REG_ACC_X_MSB, 0xFF, 0x00 }, \
{ NSA_REG_ACC_Y_LSB, 0xFF, 0x00 }, \
{ NSA_REG_ACC_Y_MSB, 0xFF, 0x00 }, \
{ NSA_REG_ACC_Z_LSB, 0xFF, 0x00 }, \