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### 电池管理芯片LTC6820关键知识点解析 #### 一、LTC6820概述 **LTC6820**是Linear Technology公司推出的一款高性能电池管理系统（BMS）专用芯片，主要用于实现电池组之间的隔离式通信与管理。该芯片支持通过单对绞线进行双向SPI（Serial Peripheral Interface）通信，可以有效提高电池管理系统的安全性和可靠性。 #### 二、主要特点 1. **isoSPI隔离通信接口**：LTC6820提供了两个隔离设备之间的双向SPI通信功能，通过单对绞线连接。这种设计消除了对变压器中心抽头的需求，并减少了电磁干扰(EMI)。 2. **高精度窗口比较器**：接收端的LTC6820内置了精密窗口比较器来检测差分信号，确保了数据传输的准确性和稳定性。 3. **外部电阻设置参数**：驱动电流和比较器阈值可以通过简单的外部电阻分压器进行设置，使系统能够根据所需的电缆长度和期望的信噪比性能进行优化。 4. **简单高效的隔离方式**：使用标准变压器即可实现简单且有效的电隔离，能够承受数百伏特的隔离电压。 5. **广泛的应用场景**：适用于工业网络、电池监控系统、远程传感器等领域，特别适合于ISO26262标准下的汽车电子系统应用。 6. **低功耗特性**：在待机模式下仅消耗2μA的电流，有助于延长电池寿命并减少能源浪费。 7. **自动唤醒检测**：具备自动检测唤醒信号的能力，简化了系统的管理和维护过程。 8. **宽工作温度范围**：能够在-40°C到125°C的温度范围内正常工作，增强了系统的环境适应性。 9. **电源电压范围宽广**：支持2.7V至5.5V的电源电压输入，兼容性好。 10. **逻辑电平接口**：能够与1.7V至5.5V范围内的各种逻辑电平兼容，便于与其他组件集成。 11. **封装形式多样**：提供16引脚QFN和MSOP封装选项，满足不同应用场景的需求。 #### 三、典型应用案例 1. **1Mbps隔离式SPI数据通信**：LTC6820支持高达1Mbps的数据传输速率，适用于高速数据交换的场景。 2. **使用标准变压器实现简单电隔离**：通过简单的脉冲变压器即可实现数百伏特的隔离效果，降低了成本同时保持了良好的隔离性能。 3. **单对绞线上双向通信**：通过单根绞线就能完成双向数据传输，大大简化了布线复杂度，降低了系统的总体成本。 4. **支持长达100米的电缆长度**：即使在长距离通信的情况下也能保持稳定的信号质量，拓宽了应用范围。 5. **极低的EMI敏感性和发射水平**：采用差分信号传输方式，有效降低了对外界电磁干扰的敏感性以及自身产生的电磁辐射。 6. **可配置为高噪声免疫或低功耗模式**：用户可以根据具体需求调整配置，以应对不同的噪声环境或降低功耗。 7. **无需软件更改**：在大多数SPI系统中使用LTC6820时无需对现有软件进行修改，简化了集成过程。 8. **符合ISO26262标准的设计**：该芯片专门针对汽车电子系统设计，符合ISO26262标准的安全要求。 #### 四、技术细节 - **信号传输机制**：LTC6820采用差分信号驱动，利用匹配的源和漏电流来消除对变压器中心抽头的需求，进一步减少EMI。 - **接口示例**：图示中展示了LTC6820作为主控器（Master）和从设备（Slave）之间的连接方式，包括必要的信号线（如MOSI、MISO、SCK、CS等）和隔离接口。 - **电缆长度与数据率的关系**：LTC6820支持的电缆长度可达100米，在不同长度的电缆上实现稳定的数据传输，同时保持较低的EMI敏感性和发射水平。 LTC6820是一款专为电池管理系统设计的高性能芯片，其独特的isoSPI隔离通信接口使得它在众多应用领域中脱颖而出，尤其是在需要高可靠性和安全性的场合。此外，它的低功耗特性、宽工作温度范围以及多种封装选择等特点也使其成为许多工程师的理想选择。

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LTC6820

6820fb

For more information www.linear.com/LTC6820

TYPICAL APPLICATION

FEATURES DESCRIPTION

isoSPI Isolated

Communications Interface

The LTC

6820 provides bidirectional SPI communications

between two isolated devices through a single twisted-

pair connection. Each LTC6820 encodes logic states into

signals that are transmitted across an isolation barrier to

another LTC6820. The receiving LTC6820 decodes the

transmission and drives the slave bus to the appropriate

logic states. The isolation barrier can be bridged by a simple

pulse transformer to achieve hundreds of volts of isolation.

The LTC6820 drives differential signals using matched

source and sink currents, eliminating the requirement

for a transformer center tap and reducing EMI. Precision

window comparators in the receiver detect the differential

signals. The drive currents and the comparator thresholds

are set by a simple external resistor divider, allowing the

system to be optimized for required cable lengths and

desired signal-to-noise performance.

Microcontroller to SPI Slave Isolated Interface Data Rate vs Cable Length

APPLICATIONS

1Mbps Isolated SPI Data Communications

Simple Galvanic Isolation Using Standard

Transformers

Bidirectional Interface Over a Single Twisted Pair

Supports Cable Lengths Up to 100 Meters

Very Low EMI Susceptibility and Emissions

Configurable for High Noise Immunity or Low Power

Engineered for ISO26262 Compliant Systems

Requires No Software Changes in Most SPI Systems

Ultralow, 2µA Idle Current

Automatic Wake-Up Detection

Operating Temperature Range: –40°C to 125°C

2.7V to 5.5V Power Supply

Interfaces to All Logic from 1.7V to 5.5V

Available in 16-Lead QFN and MSOP Packages

Industrial Networking

Battery Monitoring Systems

Remote Sensors

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and isoSPI

is a trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners. Protected by U.S. patents, including 8908779.

120Ω

100 METERS

TWISTED PAIR

LTC6820

MSTR

MOSI

MISO

SCK

MASTER

µC

SDO

SDI

SCK

120Ω

6820 TA01a

LTC6820

MSTR

MOSI

MISO

SCK

REMOTE

SLAVE IC

SDI

SDO

SCK

CABLE LENGTH (METERS)

DATA RATE (Mbps)

0.2

0.4

0.6

0.8

1.2

10 100

6820 TA01b

1.0

CAT-5 ASSUMED

LTC6820

6820fb

For more information www.linear.com/LTC6820

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

Input Supply Voltages (V

and V

DDS

) to GND ...........6V

Pin Voltages

SCK, CS, EN ...............–0.3V to V

DDS

+ 0.3V (6V Max)

IBIAS, SLOW, IP, IM .....–0.3V to V

+ 0.3V (6V Max)

All Other Pin Voltages .............................. –0.3V to 6V

Maximum Source/Sink Current

IP, IM .................................................................30mA

MOSI, MISO, SCK, CS ........................................20mA

Operating Temperature Range

LTC6820I .............................................–40°C to 85°C

LTC6820H .......................................... –40°C to 125°C

(Notes 1, 2, 3)

16 15 14 13

5 6 7 8

TOP VIEW

UD PACKAGE

16-LEAD (3mm × 3mm) PLASTIC QFN

1MOSI

MISO

SCK

SLOW

MSTR

IBIAS

ICMP

GND

DDS

POL

PHA

JMAX

= 150°C, θ

= 58.7°C/W

EXPOSED PAD (PIN 17) PCB CONNECTION TO GND IS OPTIONAL

MOSI

MISO

SCK

DDS

POL

PHA

IBIAS

ICMP

GND

SLOW

MSTR

TOP VIEW

MS PACKAGE

16-LEAD PLASTIC MSOP

JMAX

= 150°C, θ

= 120°C/W

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE

LTC6820IUD#PBF LTC6820IUD#TRPBF LGFM 16-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C

LTC6820HUD#PBF LTC6820HUD#TRPBF LGFM 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C

LTC6820IMS#PBF LTC6820IMS#TRPBF 6820 16-Lead Plastic MSOP –40°C to 85°C

LTC6820HMS#PBF LTC6820HMS#TRPBF 6820 16-Lead Plastic MSOP –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

Specified Temperature Range

LTC6820I .............................................–40°C to 85°C

LTC6820H .......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

MSOP ............................................................... 300°C

http://www.linear.com/product/LTC6820#orderinfo

LTC6820

6820fb

For more information www.linear.com/LTC6820

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full specified

temperature range, otherwise specifications are at T

= 25°C. V

= 2.7V to 5.5V, V

DDS

= 1.7V to 5.5V, R

BIAS

= 2k to 20k unless

otherwise specified. All voltages are with respect to GND.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supply

Operating Supply Voltage Range

2.7 5.5 V

DDS

IO Supply Voltage Range (Level Shifting) Affects CS, SCK, MOSI, MISO and EN Pins

1.7 5.5 V

Supply Current, READY/ACTIVE States

(Note 4)

BIAS

= 2kΩ (I

= 1mA) 1/t

CLK

= 0MHz

1/t

CLK

= 1MHz

4 4.8

5.8 mA

BIAS

= 20kΩ (I

= 0.1mA) 1/t

CLK

= 0MHz

1/t

CLK

= 1MHz

1.3 2

2.4

2.9 mA

Supply Current, IDLE State MSTR = 0V

MSTR = V

µA

DDS

IO Supply Current (Note 5) SPI Inputs and EN Pin at 0V or V

DDS

SPI Outputs Unloaded

1 µA

Biasing

BIAS

Voltage on IBIAS Pin READY/ACTIVE State

IDLE State

1.9 2.0

2.1 V

Isolated Interface Bias Current (Note 6) R

BIAS

= 2k to 20k

BIAS

Isolated Interface Current Gain V

≤ 1.6V I

= 1mA

= 0.1mA

mA/mA

Transmitter Pulse Amplitude V

= |V

– V

| V

< 3.3V

≥ 3.3V

– 1.7V

1.6

ICMP

Threshold-Setting Voltage on ICMP Pin V

TCMP

= A

TCMP

• V

ICMP

0.2 1.5 V

LEAK(ICMP)

Leakage Current on ICMP Pin V

ICMP

= 0V to V

±1 µA

LEAK(IP/IM)

Leakage Current on IP and IM Pins IDLE State, V

= V

= 0V to V

±2 µA

TCMP

Receiver Comparator Threshold Voltage

Gain

= V

/2 to V

– 0.2V,

ICMP

= 0.2V to 1.5V

0.4 0.5 0.6 V/V

Receiver Common Mode Bias IP/IM Not Driving (V

– V

ICMP

/3 – 167mV) V

Receiver Input Resistance Single-Ended to IP or IM

26 35 42 kΩ

Idle/Wake-Up (See Figures 13, 14, 15)

WAKE

Differential Wake-Up Voltage

(See Figure 13)

DWELL

= 240ns

240 mV

DWELL

Dwell Time at V

WAKE

= 240mV

240 ns

READY

Start-Up Time After Wake Detection

8 µs

IDLE

Idle Time-Out Duration

4 5.7 7.5 ms

Digital I/O

IH(CFG)

Digital Voltage Input High, Configuration

Pins (PHA, POL, MSTR, SLOW)

= 2.7V to 5.5V (POL, PHA, MSTR, SLOW)

0.7 • V

IL(CFG)

Digital Voltage Input Low, Configuration

Pins (PHA, POL, MSTR, SLOW)

= 2.7V to 5.5V (POL, PHA, MSTR, SLOW)

0.3 • V

IH(SPI)

Digital Voltage Input High, SPI Pins

(CS, SCK, MOSI, MISO)

DDS

= 2.7V to 5.5V

DDS

= 1.7V to 2.7V

0.7 • V

DDS

0.8 • V

DDS

IL(SPI)

Digital Voltage Input Low, SPI Pins

(CS, SCK, MOSI, MISO)

DDS

= 2.7V to 5.5V

DDS

= 1.7V to 2.7V

0.3 • V

DDS

0.2 • V

DDS

IH(EN)

Digital Voltage Input High, EN Pin V

DDS

= 2.7V to 5.5V

DDS

= 1.7V to 2.7V

0.85 • V

DDS

IL(EN)

Digital Voltage Input Low, EN Pin V

DDS

= 2.7V to 5.5V

DDS

= 1.7V to 2.7V

0.8

0.25 • V

DDS

Digital Voltage Output High (CS and SCK) V

DDS

= 3.3V, Sourcing 2mA

DDS

= 1.7V, Sourcing 1mA

DDS

– 0.2

DDS

– 0.25

Digital Voltage Output Low

(MOSI, MISO, CS, SCK)

DDS

= 3.3V, Sinking 3.3mA

DDS

= 1.7V, Sinking 1mA

0.2

LTC6820

6820fb

For more information www.linear.com/LTC6820

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full specified

junction temperature range, otherwise specifications are at T

= 25°C. V

= 2.7V to 5.5V, V

DDS

= 1.7V to 5.5V, R

BIAS

= 2k to 20k

unless otherwise specified. All voltages are with respect to GND.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

LEAK(DIG)

Digital Pin Input Leakage Current PHA, POL, MSTR, SLOW = 0V to V

CS, SCK, MOSI, MISO, EN = 0V to V

DDS

±1 µA

I/O

Input/Output Pin Capacitance (Note 9) 10 pF

Isolated Pulse Timing (See Figure 2)

1/2PW(CS)

Chip-Select Half-Pulse Width

120 150 180 ns

INV(CS)

Chip-Select Pulse Inversion Delay

200 ns

DEL(CS)

Chip-Select Response Delay

140 190 ns

½PW(D)

Data Half-Pulse Width

40 50 60 ns

INV(D)

Data Pulse Inversion Delay

70 ns

DEL(D)

Data Response Delay (Note 8)

75 120 ns

isoSPI™ Timing—Master (See Figures 3, 4)

CLK

SCK Latching Edge to SCK Latching Edge (Note 7) SLOW = 0

SLOW = 1

µs

MOSI Setup Time Before SCK Latching Edge (Note 8)

25 ns

MOSI Hold Time After SCK Latching Edge

25 ns

SCK Low t

CLK

= t

+ t

≥ 1µs

50 ns

SCK High t

CLK

= t

+ t

≥ 1µs

50 ns

CS Rising Edge to CS Falling Edge

0.6 µs

SCK Latching Edge to CS Rising Edge (Note 7)

1 µs

CS Falling Edge to SCK Latch Edge (Note 7)

1 µs

SCK Non-Latch Edge to MISO Valid (Note 8)

55 ns

SCK Latching Edge to Short ±1 Transmit

50 ns

CS Transition to Long ±1 Transmit

55 ns

CS Rising Edge to MISO Rising (Note 8)

55 ns

isoSPI Timing—Slave (See Figures 3, 4)

isoSPI Data Recognized to SCK

Latching Edge

(Note 8)

SLOW = 0

SLOW = 1

110

0.9

145

1.1

185

1.4

µs

SCK Pulse Width SLOW = 0

SLOW = 1

0.9

115

1.1

150

1.4

µs

SCK Non-Latch Edge to isoSPI Data Transmit (Note 8) SLOW = 0

SLOW = 1

115

0.9

145

1.1

190

1.4

µs

CS Falling Edge to SCK Non-Latch Edge PHA = 1 SLOW = 0

SLOW = 1

0.9

120

1.1

160

1.4

µs

CS Falling Edge to isoSPI Data Transmit SLOW = 0

SLOW = 1

200

1.8

265

2.2

345

2.8

µs

CS Rising Edge to SCK Latching Edge PHA = 1 SLOW = 0

SLOW = 1

0.9

120

1.1

160

1.4

µs

CS Rising Edge to MOSI Rising Edge (Note 8)

35 ns

RTN

Data Return Delay SLOW = 0

SLOW = 1

485

3.3

625

µs

Note 1:

Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive, and all voltages are referenced

to GND unless otherwise specified.

Note 3: The LTC6820I is guaranteed to meet specified performance

from –40°C to 85°C. The LTC6820H is guaranteed to meet specified

performance from –40°C to 125°C.

Note 4: Active supply current (I

) is dependent on the amount of time

that the output drivers are active on IP and IM. During those times I

will

increase by the 20 • I

drive current. For the maximum data rate 1MHz,

the drivers are active approximately 10% of the time if MSTR = 1, and 5%

LTC6820

6820fb

For more information www.linear.com/LTC6820

TYPICAL PERFORMANCE CHARACTERISTICS

Supply Current (IDLE)

vs Supply Voltage

Supply Current (IDLE)

vs Temperature

Supply Current (READY/ACTIVE)

vs Clock Frequency

Supply Current (READY)

vs Temperature

Input Voltage Threshold

(Except EN Pin)

vs Supply Voltage (V

or V

DDS

)

ELECTRICAL CHARACTERISTICS

of the time if MSTR = 0. See Applications Information section for more

detailed information.

Note 5: The IO supply pin, V

DDS

, provides power for the SPI inputs and

outputs, including the EN pin. If the inputs are near 0V or V

DDS

(to avoid

static current in input buffers) and the outputs are not sourcing current,

then I

DDS

includes only leakage current.

Note 6: The LTC6820 is guaranteed to meet specifications with R

BIAS

resistor values ranging from 2k to 20k, with 1% or better tolerance. Those

resistor values correspond to a typical I

that can range from 0.1mA

(for 20k) to 1mA (for 2k).

Note 7:

These timing specifications are dependent on the delay through

the cable, and include allowances for 50ns of delay each direction. 50ns

corresponds to 10m of CAT-5 cable (which has a velocity of propagation of

66% the speed of light). Use of longer cables would require derating these

specs by the amount of additional delay.

Note 8: These specifications do not include rise or fall time. While fall

time (typically 5ns due to the internal pull-down transistor) is not a

concern, rising-edge transition time t

RISE

is dependent on the pull-up

resistance and load capacitance. In particular, t

and t

require t

RISE

< 110ns (if SLOW = 0) for the slave’s setup and hold times. Therefore,

the recommended time constant is 50ns or less. For example, if the

total capacitance on the data pin is 25pF (including self capacitance

I/O

of 10pF), the required pull-up resistor value is R

≤ 2kΩ. If these

requirements can’t be met, use SLOW = 1.

Note 9: Guaranteed by design. Not tested in production.

= V

DDS

, unless otherwise noted.

FREQUENCY (kHz)

SUPPLY CURRENT (mA)

200 400 600 800

6820 G01

1000

= 5V, I

= 1mA

= 5V, I

= 0.1mA

= 3V, I

= 1mA

= 3V, I

= 0.1mA

MSTR = 1

TEMPERATURE (°C)

–50 –25

4.8

SUPPLY CURRENT (mA)

5.0

5.3

6820 G02

4.9

5.2

5.1

100

125

= 5V

= 3V

= 1mA

SUPPLY VOLTAGE (V)

1.5 2.5

INPUT VOLTAGE THRESHOLD (V)

0.5

1.0

1.5

2.0

4.0

3.02.0 3.5 4.0 4.5

6820 G03

5.0 5.5

3.5

3.0

2.5

ONLY

SPI PINS

HIGH

LOW

SUPPLY VOLTAGE (V)

2.5

SUPPLY CURRENT (µA)

0.5

1.0

1.5

2.0

3.0

3.5 4.0 4.5

6820 G04

5.0 5.5

2.5

SLAVE (MSTR = 0)

MASTER (MSTR = 1)

TEMPERATURE (°C)

–50

SUPPLY CURRENT (µA)

3.0

25 75

6820 G05

2.0

–25 0

50 100 125

1.0

2.5

1.5

0.5

= 5V

SLAVE (MSTR = 0)

MASTER (MSTR = 1)

Output Resistance vs Supply

Voltage (V

)

SUPPLY VOLTAGE (V)

1.5

OUTPUT RESISTANCE (Ω)

5.5

6820 G19

2.5

3.5

4.5

100

OUTPUT

SOURCING 2mA CURRENT

OUTPUT SINKING 3.3mA CURRENT

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