STM32F103VCT6原版数据手册.pdf-EasyDatasheet

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STM32F103VCT6原版数据手册.pdf-EasyDatasheet
EasyDatashee STM32F103xC. STM32F103XD, STM32F103xE Contents 2.3.29 Serial wire JTAG debug port (SWJ-DP) .24 2.3.30 Embedded trace macrocell 24 Pinouts and pin descriptions.∴…∴ n,25 345 Memory mapping 39 Electrical characteristics ,,,,,.40 5.1 Parameter conditions n■ 40 5.1.1 Minimum and maximum values 5.1.2 Typical val 40 5.1.3 Typical curves ....40 5.1. 4 Loading capacitor 40 5.1.5 Pin input voltage 40 5.1.6 Power supply scheme ...41 5.1.7 Current consumption measurement 5.2 Absolute maximum ratings 42 5.3 Operating conditions 43 5.3.1 General operating conditions 43 5.3.2 Operating conditions at power-up / power-down ,,44 5.3. 3 Embedded reset and power control block characteristics 44 5.3. 4 Embedded reference voltage 5.3.5 Supply current characteristics .45 5.3.6 External clock source characteristics 56 5.3.7 Internal clock source characteristics 5.3. 8 PLL characteristics ..63 5.3. 9 Memory characteristics 5.3.10 FSMc characteristics 5.3.11 EMC characteristics 84 5.3.12 Absolute maximum ratings (electrical sensitivity) 85 5.3.13 1 o current injection characteristics 86 5.3.14 10 port characteristIcs 87 5.3.15 NRST pin characteristics 92 5.3.16 TIM timer characteristics 93 5.3.17 Communications interfaces ■面 94 5.3.18 CAN (controller area network)interface .....103 5.3.19 12-bit ADC characteristics .,,.,104 DOCID14611 Rev 9 3/130 EasyDatashee Contents STM32F103XC. STM32F10XD. STM32F103xE 5.3.20 DAC electrical specifications 109 5.3.21 Temperature sensor characteristics 111 Package characteristics∴∴∴∴∴.∴.∴∴.112 6.1 Package mechanical data ■■ 112 6.2 Thermal characteristics 120 6.2.1 Reference document 120 6.2.2 Selecting the product temperature range 121 Part numbering n123 Revision history ,,,,,,,,,,,,,,,,,∴,.,124 4/130 DocD 14611 Rev 9 / EasyDatashee STM32F103xC. STM32F103XD, STM32F103xE List of tables List of tables Table 1. Device summary Table 2 STM32F103XC, STM32F103XD and STM32F103xE features and peripheral counts Table 3. STM32F103xx family 14 Table 4. High-density timer feature comparison Table 5. High-density STM32F103xX pin definitions Table 6 FSMC pin definition 37 Table 7 oltage characteristics .,,,42 Table 8. Current characteristics 42 Table 9. Thermal characteristics 43 Table 10. General operating conditions .43 Table 11. Operating conditions at power-up/ power-down .44 Table 12. Embedded reset and power control block characteristics 44 Table 13. Embedded internal reference voltage ..,,,.45 Table 14. Maximum current consumption in Run mode, code with data processing running from Flash Table 15. Maximum current consumption in Run mode, code with data processing running from ram 46 Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM ,48 Table 17. Typical and maximum current consumptions in Stop and Standby modes ,...,,,49 Table 18. Typical current consumption in Run mode, code with data processing running from Flash 53 Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM ..54 Table 20. Peripheral current consumption 55 Table 21. High-speed external user clock characteristics 56 Table 22. Low-speed external user clock characteristics ...57 Table 23. HSE 4-16 MHz oscillator characteristics 59 Table 24. LsE oscillator characteristics(fLSE =32.768 KHz) ...60 Table 25. hsi oscillator characteristics Table 26. LSI oscillator characteristics 62 Table 27. Low-power mode wakeup timings ...62 Table 28. PLL characteristics 63 Table 29. Flash memory characteristics 63 Table 30. Flash memory endurance and data retention Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings .,64 66 Table 32. Asynchronous non-multiplexed SRAM/P SRAM/NOR write timings Table 33. Asynchronous multiplexed PSRAM/NOR read timings ...68 T able 34. Asynchronous multiplexed P SRAM/NOR write timings 69 Table 35. Synchronous multiplexed NOR/PSRAM read timings Table 36. Synchronous multiplexed PSRAM write timings Synchronous non-multiplexed NOR/PSRAM read timings 73 Table 37 74 Table 38. Synchronous non-multiplexed PSRAM write timings Table 40. Switching characteristics for NAND Flash read and write cycle ,,,75 Table 39. Switching characteristic PC Card/C f read and write cycles 80 83 Table 41. EMs characteristics 84 Table 42. EMI characteristics 85 Table 43 ESD absolute maximum ratings .....85 DOCID14611 Rev 9 5/130 EasyDatashee List of tables STM32F103XC. STM32F10XD. STM32F103xE Table 44. Electrical sensitivities ..86 Table 45. l/0 current injection susceptibility 86 Table 46. 1/0 static characteristics .87 Table 47. Output voltage characteristics 89 Table 48. 1/0 AC characteristics Table 49. NRST pin characteristics 92 Table 50. TIMx characteristics 93 Table 52. SCL frequency(fpCLK1-=36 MHz. VDD=3.3 V) Table 51. 1=C characteristics 94 95 Table 53. SPI characteristics 96 Table 54. s characteristics 99 Table 55. Sd/MMc characteristics ,,,,,,102 Table 56. USB startup time ,,,102 Table 57. USB DC electrical characteristics 103 Table 58. USB: full-speed electrical characteristics .103 Table 59. AdC characteristics ,,104 Table 60. RAIN max for fADC =14 MHz .105 Table 61. ADC accuracy -limited test conditions ....105 Table 62 ADC accuracy 106 Table 63. Dac characteristics 109 Table 64. ts characteristics 111 Table 65. Recommended PcB design rules (0.80/0.75 mm pitch BGA) 112 Table 66. LFBGA144-144-ball low profile fine pitch ball grid array, 10 X 10 mm 0. 8 mm pitch, package data ...113 Table 67. LFBGA100-10 x 10 mm low profile fine pitch ball grid array package mechanical data 114 Table 68. WLCSP, 64-ball 4.466x 4 395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data Table 69. Recommended PCB design rules(0.5mm pitch BGA) 116 Table 70. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data ,117 Table 71. LQPF100-14x 14 mm 100-pin low-profile quad flat package mechanical data.... 118 Table 72. LQFP64-10 x 10 mm 64 pin low-profile quad flat package mechanical data 119 Table 73. Package thermal characteristics 120 Table 74. Ordering information scheme 123 6/130 DocID14611 Rev 9 / EasyDatashee STM32F103xC. STM32F103XD, STM32F103xE List of figures List of figures Figure 1. STM32F103XC, STM32F103xD and stM32F103XE performance line block diagram..12 Figure 2. Clock tree Figure 3. STM32F103XC and STM32F103XE performance line BGA144 ballout .,.25 Figure 4. STM32F103xC and STM32F103XE performance line BGA100 ballout 26 Figure 5. STM32F103XC and STM32F103xE performance line LQFP 144 pinout 27 Figure 6. STM32F103xC and sTM32F103xE performance line LQFP100 pinout 28 Figure 7. STM32F103XC and StM32F103xE performance line LQFP64 pinout Figure 8. STM32F103XC and STM32F103XE performance line WLCSP64 ballout ball side 30 Figure 9 Memory map .39 Figure 10. Pin loading conditions 40 Figure 11. Pin input voltage .40 Figure 13. Current consumption measurement scheme Figure 12. Power supply scheme Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from ram, peripherals enabled ..47 Figure 15. Typical current consumption in Run mode versus frequency(at 3.6 v)- code with data processing running from RAM, peripherals disabled Figure 16. Typical current consumption on VBAT With RTC on VS temperature at different VbaT values 49 Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different∨ Dp values,… 50 Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different Vpp values Figure 19. Typical current consumption in Standby mode versus temperature at different VoD values 2 Figure 20. High-speed external clock source AC timing diagram 57 Figure 21. Low-speed external clock source AC timing diagram .,,,,,58 Figure 22. Typical application with an 8 MHz crystal 59 Figure 23. Typical application with a 32.768 kHz crystal Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 65 Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms 66 Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms ..,..67 Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms 68 Figure 28. Synchronous multiplexed NOR/PSRAM read timings Figure 29. Synchronous multiplexed PSRAM write timings 72 Figure 30. Synchronous non-multiplexed NOR/P SRAM read timings 74 Figure 31. Synchronous non- multiplexed PSRAM write timings 75 Figure 32. PC Card/CompactFlash controller waveforms for common memory read access 76 Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read Ccess Figure 33. PC Card/ CompactFlash controller waveforms for common memory write access access 78 Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access 79 Figure 36. PC Card/CompactFlash controller waveforms for lo space read access 79 Figure 37. PC Card/CompactFlash controller waveforms for VO space write access 80 Figure 38. NAND controller waveforms for read access .....82 DocD 14611 Rev 9 7/130 EasyDatashee List of figures STM32F103XC. STM32F10XD. STM32F103xE Figure 39. NAND controller waveforms for write access 82 Figure 40. NAND controller waveforms for common memory read access 82 Figure 41. NAND controller waveforms for common memory write access ..83 Figure 42. Standard 1/0 input characteristics- CMOS port 88 Figure 43. Standard l/o input characteristics- TTL port 88 Figure 44. 5V tolerant 1/0 input characteristics- CMOS port 88 Figure 45. 5V tolerant l O input characteristics- ttl port Figure 46. 1/0 AC characteristics definition 92 Figure 47. Recommended nrst pin protection Figure 48. 2C bus AC waveforms and measurement circuit .92 95 97 Figure 50. SP! timing diagram -slave mode and CPHA=1(1) 97 Figure 51. SPI timing diagram -master mode(1) 98 Figure 52. 12s slave timing diagram(Philips protocol) ( 1) 100 Figure 53. 1-S master timing diagram(Philips protocol) 100 Figure 54. sdio high-speed mode 101 Figure 55. sd default mode Figure 56. USB timings: definition of data signal rise and fall time .....103 Figure 57. ADC accuracy characteristics 106 Figure 58. Typical connection diagram using the ADC ,,,,107 Figure 59. Power supply and reference decoupling(VREF+ not connected to VDDA 107 Figure 60. Power supply and reference decoupling(VREF connected to VdpA .108 Figure 61. 12-bit buffered /non-buffered dAc 110 Figure 62. BGA pad footprint igure 63. LFBGA144-144-ball low profile fine pitch ball grid array, 10 x 10 nnl ,112 Fic 0.8 mm pitch, package outli 113 Figure 64. LFBGA100-10X 10 mm low profile fine pitch ball grid array package outline 114 Figure 65. WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch wafer-level chip-scale package outline 115 Figure 66. BGA pad footprint 116 Figure 67. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline ,117 Figure 68. Recommended footprint (1) 117 Figure 69. LQFP100, 14x 14 mm 100-pin low-profile quad flat package outline .....118 Figure 70. Recommended footprint (1) .118 Figure72. Recommended footprint(()∴…. ofile Figure 71. LQFP64-10x 10 mm 64 pin low-pI quad flat package outline .,.,,119 119 Figure 73. LQFP100 PD max vs TA 122 8/130 DocID14611 Rev 9 / Easy Datasheet STM32F103xC. STM32F103XD, STM32F103xE Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103XC, STM32F103XD and STM32F103XE high-density performance line microcontrollers For more details on the whole st microelectronics stm32F103xx famil please refer to Section 2. 2: Full compatibility throughout the family The high-density STM32F103xX datasheet should be read in conjunction with the STM32F10xXx reference manual For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10XXX Flash programming manual The reference and flash programming manuals are both available from the STMicroelectronicswebsitewwwst.com For in formation on the Cortey _M3 core please refer to the Coro_M3 Technical Reference Manualavailablefromthewww.armcomwebsiteatthefollowingaddress http:/infocenter.arm.com Cortex Intelligent Processors by ARM ARMI DocD 14611 Rev 9 9/130 EasyDatashee Description STM32F103XC. STM32F103xD. STM32F103xE 2 Description The STM32F103XC, STM32F103XD and STM32F103XE performance line family incorporates the high-performance ARM Cortex-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories(Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced lOs and peripherals connected to two APB buses. All devices offer three 12-bit ADCS, four general-purpose 16- bit timers plus two PWm timers, as well as standard and advanced communication interfaces: up to two I-Cs, three SPls, two I-Ss, one SDIo, five USARTS, an USB and a CAN The STM32F103xx high-density performance line family operates in the -40 to +105C temperature range, from a 2.0 to 3.6 V power supply. a comprehensive set of power-saving mode allows the design of low-power applications These features make the STM32F103xX high-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems video intercom, and HVAC 10/130 DocID14611 Rev 9 /

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