VHDL语言编写红绿灯代码

LIBRARY Ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY deng1 IS
Port( clk : in std_logic;
       ra,rb,ya,yb,ga,gb : out std_logic );
END deng1;
Architecture one of deng1 is
  type state is (S0,S1,S2,S3);
    signal presentstate,nextstate : state;
    signal tmp30 : std_logic_vector(5 downto 0);
    signal tmp5 : std_logic_vector(2 downto 0);
    signal timeout30,timeout5 : std_logic;
    signal rst30,rst5 : std_logic :='0';
    signal en30,en5 : std_logic :='0';
    signal q : std_logic_vector(2 downto 0);
    signal sec : std_logic;
 BEGIN
  process(clk)
     begin
     if clk'event and clk='1' then q<=q+1; 
     end if;
     sec<=q(2); 
  end process;
reg: process(sec)
BEGIN
 if sec'event and sec='1' then
 presentstate<=nextstate; 
 end if;
 end process reg;