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Application Report

SPRAAR7A–January 2013

USB 2.0 Board Design and Layout Guidelines

DSPS Applications............................................................................................................................

ABSTRACT

This application report discusses schematic guidelines when designing a universal serial bus (USB)

system.

Contents

1 Background .................................................................................................................. 1

2 USB PHY Layout Guide .................................................................................................... 2

3 Electrostatic Discharge (ESD) ............................................................................................. 8

4 References ................................................................................................................. 10

List of Figures

1 Suggested Array Capacitors and a Ferrite Bead to Minimize EMI ................................................... 2

2 Four-Layer Board Stack-Up ............................................................................................... 3

3 USB Connector.............................................................................................................. 4

4 3W Spacing Rule ........................................................................................................... 4

5 Power Supply and Clock Connection to the USB PHY ................................................................ 5

6 USB PHY Connector and Cable Connector ............................................................................. 6

7 Do Not Cross Plane Boundaries .......................................................................................... 7

8 Do Not Overlap Planes..................................................................................................... 7

9 Do Not Violate Image Planes.............................................................................................. 8

List of Tables

1 Background

Clock frequencies generate the main source of energy in a USB design. The USB differential DP/DM pairs

operate in high-speed mode at 480 Mbps. System clocks can operate at 12 MHz, 48 MHz, and 60 MHz.

The USB cable can behave as a monopole antenna; take care to prevent RF currents from coupling onto

the cable.

When designing a USB board, the signals of most interest are:

• Device interface signals: Clocks and other signal/data lines that run between devices on the PCB.

• Power going into and out of the cable: The USB connector socket pin 1 (VBUS ) may be heavily

filtered and need only pass low frequency signals of less than ~100 KHz. The USB socket pin 4

(analog ground) must be able to return the current during data transmission, and must be filtered

sparingly.

• Differential twisted pair signals going out on cable, DP and DM: Depending upon the data transfer rate,

these device terminals can have signals with fundamental frequencies of 240 MHz (high speed), 6

MHz (full speed), and 750 kHz (low speed).

• External crystal circuit (device terminals XI and X0): 12 MHz, 19.2 MHz, 24 MHz, and 48 MHz

fundamental. When using an external crystal as a reference clock, a 24 MHz and higher crystal is

highly recommended.

All trademarks are the property of their respective owners.

SPRAAR7A–January 2013 USB 2.0 Board Design and Layout Guidelines

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Analog

PowerSupply

SoCBoard

FerriteBead

Digital

PowerSupply

FerriteBead

0.1µF

0.01µF

0.001µF

10µF

0.1µF

0.01µF

0.001µF

10µF

USB PHY Layout Guide

www.ti.com

2 USB PHY Layout Guide

The following sections describe in detail the specific guidelines for USB PHY Layout.

2.1 General Routing and Placement

Use the following routing and placement guidelines when laying out a new design for the USB physical

layer (PHY). These guidelines help minimize signal quality and electromagnetic interference (EMI)

problems on a four-or-more layer evaluation module (EVM).

• Place the USB PHY and major components on the un-routed board first. For more details, see

Section 2.2.3.

• Route the high-speed clock and high-speed USB differential signals with minimum trace lengths.

• Route the high-speed USB signals on the plane closest to the ground plane, whenever possible.

• Route the high-speed USB signals using a minimum of vias and corners. This reduces signal

reflections and impedance changes.

• When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90°

turn. This reduces reflections on the signal traces by minimizing impedance discontinuities.

• Do not route USB traces under or near crystals, oscillators, clock signal generators, switching

regulators, mounting holes, magnetic devices or IC’s that use or duplicate clock signals.

• Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is

unavoidable, then the stub should be less than 200 mils.

• Route all high-speed USB signal traces over continuous planes (V

or GND), with no interruptions.

Avoid crossing over anti-etch, commonly found with plane splits.

2.2 Specific Guidelines for USB PHY Layout

The following sections describe in detail the specific guidelines for USB PHY Layout.

2.2.1 Analog, PLL, and Digital Power Supply Filtering

To minimize EMI emissions, add decoupling capacitors with a ferrite bead at power supply terminals for

the analog, phase-locked loop (PLL), and digital portions of the chip. Place this array as close to the chip

as possible to minimize the inductance of the line and noise contributions to the system. An analog and

digital supply example is shown in Figure 1. In case of multiple power supply pins with the same function,

tie them up to a single low-impedance point in the board and then add the decoupling capacitors, in

addition to the ferrite bead. This array of caps and ferrite bead improve EMI and jitter performance. Take

both EMI and jitter into account before altering the configuration.

Figure 1. Suggested Array Capacitors and a Ferrite Bead to Minimize EMI

USB 2.0 Board Design and Layout Guidelines SPRAAR7A–January 2013

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Signal1

PowerPlane

GNDPlane

Signal2

www.ti.com

USB PHY Layout Guide

Consider the recommendations listed below to achieve proper ESD/EMI performance:

• Use a 0.01 μF cap on each cable power VBUS line to chassis GND close to the USB connector pin.

• Use a 0.01 μF cap on each cable ground line to chassis GND next to the USB connector pin.

• If voltage regulators are used, place a 0.01 μF cap on both input and output. This is to increase the

immunity to ESD and reduce EMI. For other requirements, see the device-specific datasheet.

2.2.2 Analog, Digital, and PLL Partitioning

If separate power planes are used, they must be tied together at one point through a low-impedance

bridge or preferably through a ferrite bead. Care must be taken to capacitively decouple each power rail

close to the device. The analog ground, digital ground, and PLL ground must be tied together to the low-

impedance circuit board ground plane.

2.2.3 Board Stackup

Because of the high frequencies associated with the USB, a printed circuit board with at least four layers

is recommended; two signal layers separated by a ground and power layer as shown in Figure 2.

Figure 2. Four-Layer Board Stack-Up

The majority of signal traces should run on a single layer, preferably SIGNAL1. Immediately next to this

layer should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in

the ground or power plane. When running across split planes is unavoidable, sufficient decoupling must

be used. Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.

2.2.4 Cable Connector Socket

Short the cable connector sockets directly to a small chassis ground plane (GND strap) that exists

immediately underneath the connector sockets. This shorts EMI (and ESD) directly to the chassis ground

before it gets onto the USB cable. This etch plane should be as large as possible, but all the conductors

coming off connector pins 1 through 6 must have the board signal GND plane run under. If needed, scoop

out the chassis GND strap etch to allow for the signal ground to extend under the connector pins. Note

that the etches coming from pins 1 and 4 (VBUS power and GND) should be wide and via-ed to their

respective planes as soon as possible, respecting the filtering that may be in place between the connector

pin and the plane. See Figure 3 for a schematic example.

Place a ferrite in series with the cable shield pins near the USB connector socket to keep EMI from getting

onto the cable shield. The ferrite bead between the cable shield and ground may be valued between 10 Ω

and 50 Ω at 100 MHz; it should be resistive to approximately 1 GHz. To keep EMI from getting onto the

cable bus power wire (a very large antenna) a ferrite may be placed in series with cable bus power,

VBUS, near the USB connector pin 1. The ferrite bead between connector pin 1 and bus power may be

valued between 47 Ω and approximately 1000 Ω at 100 MHz. It should continue being resistive out to

approximately 1 GHz, as shown in Figure 3.

SPRAAR7A–January 2013 USB 2.0 Board Design and Layout Guidelines

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