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LPDDR4 SDRAM products require a well-designed system board environment to reliably support high-speed/low-power applications. Proven layout and routing techniques are required for embedded and mobile designs using point-to-point DRAM interfaces in side-by-side (non-PoP) configurations. Derived from transmission line theory and Micron design experience, the guidelines presented in this technical note can enhance signal integrity (SI) and reduce noise for point-to-point design
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Technical Note
LPDDR4/LPDDR4X Point-to-Point, Non-PoP, Design Guidelines
Introduction
LPDDR4 SDRAM products require a well-designed system board environment to relia-
bly support high-speed/low-power applications.
Proven layout and routing techniques are required for embedded and mobile designs
using point-to-point DRAM interfaces in side-by-side (non-PoP) configurations. De-
rived from transmission line theory and Micron design experience, the guidelines pre-
sented in this technical note can enhance signal integrity (SI) and reduce noise for
point-to-point (as well as point-to-multipoint) designs.
The guidelines and examples in this technical note represent one of several acceptable
methods and may not be applicable for all designs.
For more information, refer to these additional Micron technical notes that also focus
on point-to-point SDRAM design, layout and simulation techniques:
• TN-52-02: Point-to-Point System Design: Layout and Routing Tips for LPDDR2 and
LPDDR3 Devices
• TN-41-13: DDR3 Point-to-Point Design Support
Table 1: Definitions
Term Definition
DDP Dual-die package
Power delivery Power and ground layout and decoupling techniques used to improve signal integrity
SDP Single-die package
SSO Simultaneous switching outputs
V
DDQ
DQ and I/O signal power; the two are equivalent unless otherwise noted
V
DD
Digital power for the device core
V
REFDQ
Reference for DQ input buffers
V
SS
Digital ground
V
SSQ
DQ and signal ground; the two are equivalent unless otherwise noted
Micron Confidential and Proprietary
TN-53-06: LPDDR4/LPDDR4X Point-to-Point Design Guidelines
Introduction
CCMTD-1725822587-9939
tn5306_lpddr4_design_guidelines.pdf - Rev. F 3/18 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. All
information discussed herein is provided on an "as is" basis, without warranties of any kind.

LPDDR4-to-LPDDR3 Comparison
Substantial architecture differences exist between LPDDR4 and LPDDR3 technologies.
Both LPDDR4 and LPDDR3 products support a source-synchronous data strobe where
data is transferred on both the leading and trailing strobe edges.
When designing a point-to-point memory system, the major differences to be aware of
between LPDDR4 and LPDDR3 products are:
• LPDDR4 products increase in bandwidth from 1866 MT/s to 3733 MT/s and beyond
using newer LVSTL signaling techniques
• LPDDR4 products are configured as one or more x16 channels
The following table provides a highlighted comparison of the devices.
Table 2: Key Feature Comparison
Feature LPDDR4 LPDDR3
Density Up to 32Gb Up to 32Gb
Prefetch size 16n (512-bit total) 8n (256-bit total)
Core voltage (V
DD
) 1.1V 1.2V
1.8V 1.8V
I/O voltage 1.1V or 0.6V 1.2V
Maximum clock
frequency/data rate
2133 MHz/DDR4266 800 MHz/DDR1600; 933 MHz/DDR1866
Burst lengths 16, 32 8
Configurations 2 channel x16 per die, 1 channel x16 per
die
x16, x32
Address command
signals
CA[5:0] 14 pins (multiplexed command and ad-
dress)
Address/command data rate SDR (rising clock edge only) DDR (rising and falling clock edge)
PASR Full-, half- or quarter-array with individual
bank and segment masking for partial
bank modes
Individual bank and segment masking for
partial bank modes
Drive strength RZQ/6 34 ohm
RZQ/5 40 ohm
RZQ/4 48 ohm
RZQ/3 –
RZQ/2 –
RZQ/1 –
ZQ calibration for ± xx% accuracy (TBD) ZQ calibration for ± 10% accuracy
Per bank refresh Yes Yes
Output driver LVSTL, V
SSQ
terminated HSUL_12
DPD No Yes
DLL/ODT No/Yes (ODT on DQ, DQS, DM and CA) No/Yes (ODT on DQ, DQS, DM)
Package options POP, MCP, discrete POP, MCP, discrete
Micron Confidential and Proprietary
TN-53-06: LPDDR4/LPDDR4X Point-to-Point Design Guidelines
LPDDR4-to-LPDDR3 Comparison
CCMTD-1725822587-9939
tn5306_lpddr4_design_guidelines.pdf - Rev. F 3/18 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.

LPDDR4 Block Diagrams
The following block diagrams illustrate the basic data bus topology used for the simula-
tion examples presented in this guide. The guidelines derived from these simulations
on the DDR data bus can then easily be applied to the SDR command/address (CA) bus.
Only one of the two 2GB DDP LPDDR4 components is simulated; the other 2GB com-
ponent will be the same. Also, only the READ cycle is simulated. The WRITE cycle
should have similar values, assuming that the memory controller data bus drivers are
well matched to the DRAM drivers.
Figure 1: Example DRAM Subsystem Arrangement – Two 2GB DDP 200-Ball Components
LPDDR4
Channel A
LPDDR4
Channel B
Die 0
RESET_n
CS0_A
CKE0_A CKE0_B
CS0_B
CK_t_A
CK_c_A
CA[5:0]_A
CK_t_B
CK_c_B
CA[5:0]_B
DMI[1:0]_A
DQ[15:0]_A
DQS[1:0]_t_A
DQS[1:0]_c_A
DMI[1:0]_B
DQ[15:0]_B
DQS[1:0]_t_B
DQS[1:0]_c_B
ODT_CA_A ODT_CA_B
ZQ0
RZQ
V
DDQ
RZQ
V
DDQ
V
SS
V
SS
LPDDR4
Channel A
LPDDR4
Channel B
Die 1
CS1_A
CKE1_A CKE1_B
CS1_B
ZQ1
V
DD1
V
DD2
V
SS
V
DDQ
ODTcaODTca
SoC Flash
LP4LP4
Micron Confidential and Proprietary
TN-53-06: LPDDR4/LPDDR4X Point-to-Point Design Guidelines
LPDDR4 Block Diagrams
CCMTD-1725822587-9939
tn5306_lpddr4_design_guidelines.pdf - Rev. F 3/18 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.

Figure 2: Dual 2GB (16Gb) = 4GB LP4 Subsystem (Read Only)
SoC Memory Controller
CA
CS0
(Rank0)
CS1
(Rank1)
LPDDR4 DDP
200-Ball FBGA
Ch 1
DQ[31:16]
Ch 0
DQ[15:0]
LPDDR4
Die
LP4 DDP
SoC
DQ
DQ
LPDDR4
Die
Read CS0
Read CS1
Memory interface x32
8Gb
x16
Ch A
8Gb
x16
Ch A
8Gb
x16
Ch B
8Gb
x16
Ch B
Micron Confidential and Proprietary
TN-53-06: LPDDR4/LPDDR4X Point-to-Point Design Guidelines
LPDDR4 Block Diagrams
CCMTD-1725822587-9939
tn5306_lpddr4_design_guidelines.pdf - Rev. F 3/18 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.

Programmable Drive Strength and Bus Topology
Because LPDDR4 products are designed for point-to-point topology applications, a
programmable drive strength option is provided to match memory DQ/DQS drive
strength to the impedance of the data bus traces, eliminating the need for a termination
voltage supply (V
TERM
) and a series-termination resistor.
Six drive strengths are supported: RZQ/6Ω, RQZ/5Ω, RZQ/4Ω, RZQ/3Ω, RZQ/2Ω, and
RZQ/1Ω.
In low-power, short-channel-trace, point-to-point systems, termination (ODT) can of-
ten be eliminated if the trace Z
0
and drive impedance are carefully matched.
This section contains simulation results for READ operations that assess signal integrity
[Data Bus DQ Read Eye Diagrams With ODT (Clock = 1600 MHz)]. The figure shows re-
sults for the controller and DRAM positioned 10mm, 20mm, 30mm and 45mm apart.
The interconnect between the controller and the DRAM should be designed so that its
characteristic impedance is approximately 50Ω, nominally. The set up and models used
are detailed below:
• Databus configuration: Point-to-two-point (controller to DDP package)
• DRAM driver model: version 5.0 Power Aware IBIS model
• DRAM package model: 200-ball RLC model extracted by Apex Quasi-Static 3D field
solver
• DRAM driver V
OH
setting: V
DDQ
/3.0
• PCB model: HSPICE frequency dependent W-element model with 10 coupled lines
• PCB target impedance: 50Ω ±10%
• Controller package model: 200-ball RLC model (no controller package model availa-
ble yet)
• Controller input capacitance load: 1.5pF
• Byte simulated: DQ[7:0], DQS0/DQS0# of the top die (which has the highest level of
crosstalk)
• Eye measurement method: Aperture DC window (V
REF
±60mV) with V
REF
centering
• Pass/Fail criteria: Aperture DC ≥60% UI, voltage margin ≥ 15mV
• Simulation methodology: Design of experiment (DOE) with JMP statistical analysis
tool
• Simulation tool: Synopsys HSPICE 2014.09-SP2 ver. J (latest version)
Because LPDDR4 products are used in point-to-point applications, data eye apertures
for WRITE operations will be similar to those shown for READ operations, providing
that the drivers for the memory controller have similar characteristics to the DRAM
drivers. System engineers can also take advantage of on-die termination (ODT) options
(R
TT
= 120/240) for higher speed or for more heavily loaded point to multipoint systems
to improve signal integrity.
For the figures in this section:
• AptACDC is the AC DC aperture (the opening of the data eye)
• RailOShoot is the rail overshoot (measures peak distortion)
• RailUShoot is the rail undershoot (measures peak distortion)
Analysis covers all components in the memory/controller signaling channel (including
I/O driver, memory package, PCB traces, controller package and receiver).
Micron Confidential and Proprietary
TN-53-06: LPDDR4/LPDDR4X Point-to-Point Design Guidelines
Programmable Drive Strength and Bus Topology
CCMTD-1725822587-9939
tn5306_lpddr4_design_guidelines.pdf - Rev. F 3/18 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
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