################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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Xilinx cordic Rotate 工程文件
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Xilinx cordic Rotate 工程文件,初步使用Cordic IP 内核实现了输入向量的旋转。
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Xilinx cordic Rotate 工程文件 (206个子文件)
__synthesis_is_complete__ 0B
xsim.ini.bak 23KB
elaborate.bat 1KB
compile.bat 1020B
simulate.bat 822B
runme.bat 229B
xsim_2.c 73KB
xsim_1.c 72KB
xsim.dbg 10KB
cordic_0.dcp 988KB
cordic_0.dcp 968KB
cordic_0.dcp 967KB
cordic_0.dcp 967KB
cordic_0.dcp 967KB
cordic_0.dcp 964KB
hs_err_pid2796.dmp 553KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
simulate.do 494B
simulate.do 488B
simulate.do 488B
elaborate.do 366B
simulate.do 193B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
simulate.do 11B
xsimk.exe 1001KB
run.f 1KB
run.f 1KB
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 65B
xsim.ini 23KB
xsim.ini 22KB
xsimSettings.ini 1KB
webtalk.jou 862B
webtalk_20184.backup.jou 862B
vivado.jou 718B
ISEWrap.js 7KB
rundef.js 1KB
runme.log 51KB
elaborate.log 11KB
webtalk.log 931B
webtalk_20184.backup.log 931B
xvlog.log 394B
compile.log 394B
xsimkernel.log 342B
hs_err_pid2796.log 143B
simulate.log 50B
xsimcrash.log 0B
xvhdl.log 0B
cordic_rotate.lpr 290B
xsim.mem 366KB
xsim_0.win64.obj 968KB
xsim_2.win64.obj 56KB
xsim_1.win64.obj 55KB
elab.opt 378B
vivado.pb 75KB
xelab.pb 18KB
xvlog.pb 694B
cordic_0_utilization_synth.pb 268B
xvhdl.pb 16B
cordic_rotate_tb_vlog.prj 309B
cordic_rotate_tb_vhdl.prj 174B
vhdl.prj 109B
xsim.reloc 304KB
xsim.rlx 1KB
xil_defaultlib.rlx 556B
cordic_0_utilization_synth.rpt 11KB
.vivado.begin.rst 180B
.vivado.end.rst 0B
.Vivado_Synthesis.queue.rst 0B
xsim.rtti 537B
glbl.sdb 4KB
cordic_rotate_tb.sdb 2KB
cordic_rotate.sdb 1KB
cordic_0.sh 8KB
cordic_0.sh 6KB
cordic_0.sh 6KB
cordic_0.sh 6KB
cordic_0.sh 5KB
cordic_0.sh 5KB
cordic_0.sh 5KB
cordic_0.sh 5KB
ISEWrap.sh 2KB
runme.sh 1KB
xsim.svtype 66B
cordic_0.tcl 9KB
xsim_webtalk.tcl 4KB
cmd.tcl 464B
cordic_rotate_tb.tcl 460B
cordic_v6_0_changelog.txt 7KB
README.txt 3KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
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