用FPGA利用xilinx自带的IP核实现反正切运算

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FPGA,反正切

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用FPGA利用xilinx自带的IP核实现反正切运算（734个子文件）

_1 8.87MB

_1 154KB

_1 5KB

diveded.asy 633B

angle.asy 522B

divided.asy 519B

angle1.asy 441B

fixed.asy 432B

lll.asy 430B

sqrt.asy 425B

jkjlk.asy 350B

float.asy 349B

m_00000000002142219875_3054175157.c 180KB

m_00000000002142219875_3054175157.c 172KB

m_00000000001347610518_3767955098.c 156KB

m_00000000001347610518_3767955098.c 147KB

m_00000000001650716143_3096640595.c 82KB

m_00000000001784029001_3251147557.c 65KB

m_00000000001108370118_3265217243.c 60KB

m_00000000001784029001_3251147557.c 60KB

m_00000000001108370118_3265217243.c 60KB

m_00000000001108370118_3265217243.c 55KB

m_00000000001034053449_2416686687.c 53KB

m_00000000003063447631_2704097811.c 49KB

m_00000000001773747898_0266641171.c 47KB

m_00000000001773747898_0266641171.c 46KB

m_00000000000786609748_1994578349.c 26KB

m_00000000000932086926_1994578349.c 26KB

m_00000000001835017794_2030189609.c 23KB

m_00000000004221170615_0679316750.c 19KB

m_00000000000905158087_1335204964.c 13KB

m_00000000002601448656_3367321443.c 12KB

m_00000000001151294466_1457637995.c 10KB

m_00000000000598825879_0453253259.c 9KB

m_00000000000950279619_0574535450.c 8KB

m_00000000004134447467_2073120511.c 8KB

m_00000000001023468445_2996216107.c 8KB

m_00000000001059043257_3217349443.c 7KB

tb_gradient_final_isim_beh.exe_main.c 7KB

tb_gradient_final_2_isim_beh.exe_main.c 7KB

m_00000000003405408344_3841093685.c 7KB

m_00000000002444920515_2091797430.c 7KB

m_00000000001508379050_3852734344.c 6KB

m_00000000004270224262_1143447481.c 5KB

m_00000000001844249156_3898728092.c 2KB

m_00000000003848737514_1058825862.c 2KB

m_00000000001844249156_2027864845.c 2KB

m_00000000001844249156_3898728092.c 2KB

m_00000000003848737514_1058825862.c 2KB

m_00000000001844249156_2027864845.c 2KB

m_00000000003848737514_1058825862.c 2KB

m_00000000003927721830_1593237687.c 2KB

m_00000000003317509437_1759035934.c 2KB

m_00000000003927721830_1593237687.c 2KB

m_00000000003317509437_1759035934.c 2KB

m_00000000001645654456_2595668066.c 2KB

m_00000000003927721830_1593237687.c 2KB

m_00000000003317509437_1759035934.c 2KB

tb_sqrt_isim_beh.exe_main.c 2KB

m_00000000000909115699_2771340377.c 2KB

m_00000000000236260522_2449448540.c 2KB

tb_gradient_isim_beh.exe_main.c 1KB

m_00000000003427265135_0239287652.c 1KB

m_00000000001695995990_3921294355.c 1KB

m_00000000003427265135_0239287652.c 1KB

m_00000000001695995990_3921294355.c 1KB

m_00000000000852205411_2595668066.c 1KB

m_00000000001695995990_3921294355.c 1KB

coregen.cgp 236B

fuseRelaunch.cmd 311B

isim.cmd 44B

gradient_final.cmd_log 3KB

float_3.cmd_log 2KB

float_1.cmd_log 264B

共 734 条

DS335 March 1, 2011 www.xilinx.com 1

Product Specification

of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Introduction

The Xilinx® Floating-Point core provides designers

with the means to perform floating-point arithmetic on

an FPGA device. The core can be customized for

operation, word length, latency, and interface.

Features

• Available for Kintex

™

-7, Virtex

-7, Virtex-6,

Virtex-5, Virtex-4, Spartan

-6, Spartan-3/XA,

Spartan-3E/XA, Spartan-3A/AN/3A DSP/XA

FPGAs

• Supported operators:

•multiply

• add/subtract

•divide

• square-root

•comparison

• conversion from floating-point to fixed-point

• conversion from fixed-point to floating-point

• conversion between floating-point types

•Compliance with IEEE-754 Standard (with only

minor documented deviations)

• Parameterized fraction and exponent wordlengths

•Use of XtremeDSP

™

slice for multiply

• Use of XtremeDSP slice for single and double

precision add/subtract operations on Virtex and

Kintex families

• Optimizations for speed and latency

• Fully synchronous design using a single clock

• For use with CORE Generator™ software which is

available in the Xilinx ISE

13.1 software

LogiCORE IP Floating-Point

Operator v5.0

DS335 March 1, 2011 Product Specification

LogiCORE IP Facts Table

Core Specifics

Supported

Device Family

1. For a complete listing of supported devices, see the release

notes for this core.

Virtex-7, Kintex-7,

Virtex-6, Virtex-5, Virtex-4,

Spartan

-6, Spartan-3/XA, Spartan-3E/XA,

Spartan-3A/3AN/3A DSP/XA

Supported User

Interfaces

N/A

Provided with Core

Documentation Product Specification

Design Files Netlist

Example Design Not Provided

Test Bench Not Provided

Constraints File N/A

Simulation

Model

Verilog, VHDL

Tested Design Tools

Design Entry

Tools

CORE Generator 13.1

Simulation

Mentor Graphics ModelSim 6.6d,

Cadence Incisive Enterprise

Simulator (IES) 10.2,

Synopsys VCS and VCS MX 2010.06,

ISIM 13.1

Synthesis Tools Not Provided

Support

Provided by Xilinx, Inc.

LogiCORE IP Floating-Point Operator v5.0

2 www.xilinx.com DS335 March 1, 2011

Product Specification

Overview

The Xilinx Floating-Point core allows a range of floating-point arithmetic operations to be performed

on FPGA. The operation is specified when the core is generated, and each operation variant has a

common interface. This interface is shown in Figure 1. When a user selects an operation that requires

only one operand, the B input is omitted.

Functional Description

The floating-point and fixed-point representations employed by the core are described in

Floating-Point Number Representation and Fixed-Point Number Representation.

Floating-Point Number Representation

The core employs a floating-point representation that is a generalization of the IEEE-754 Standard to

allow for non-standard sizes [Ref 1]. When standard sizes are chosen, the format and special values

employed are identical to those described by the IEEE-754 Standard.

Two parameters have been adopted for the purposes of generalizing the format employed by the

Floating-Point core. These specify the total format width and the width of the fractional part. For

standard single precision types, the format width is 32 bits and fraction width 24 bits. In the following

description, these widths are abbreviated to and , respectively.

A floating-point number is represented using a sign, exponent, and fraction (which are denoted as ’s,’

’E,’ and , respectively).

The value of a floating-point number is given by:

The binary bits, , have weighting , where the most significant bit is a constant 1. As such, the

combination is bounded such that and the number is said to be normalized. To

provide increased dynamic range, this quantity is scaled by a positive or negative power of 2 (denoted

here as E). The sign bit provides a value that is negative when , and positive when .

X-Ref Target - Figure 1

Figure 1: Block Diagram of Generic Floating-Point Binary Operator Core

Floating -Point

Operator

Result = A op B

OPERATION

OPERATION_ND

OPERATION_RFD

SCLR

CLK

RESULT

UNDERFLOW

OVERFLOW

INVALID_OP ER ATION

DIVIDE_BY_ZERO

RDY

DS335_01_021508

b

1–

v1–

b

1–

i–

1 b

b

p1–

2

s1=

s0=

DS335 March 1, 2011 www.xilinx.com 3

Product Specification

LogiCORE IP Floating-Point Operator v5.0

The binary representation of a floating-point number contains three fields as shown in Figure 2.

As is a constant, only the fractional part is retained, that is, . This requires only

bits. Of the remaining bits, one bit is used to represent the sign, and bits represent

the exponent.

The exponent field, , employs a biased unsigned integer representation, whose value is given by:

The index, i, of each bit within the exponent field is given in Figure 2.

The signed value of the exponent, , is obtained by removing the bias, that is, .

In reality, is not the wordlength of the fraction, but the fraction with the hidden bit, , included.

This terminology has been adopted to provide commonality with that used to describe fixed-point

parameters (as employed by Xilinx System Generator

™

for DSP).

Special Values

A number of values for , and have been reserved for representing special numbers, such as Not

a Number (NaN), Infinity (

), Zero (0), and denormalized numbers (see Denormalized Numbers for

an explanation of the latter). These special values are summarized in Table 1.

Note that in Table 1 the sign bit is undefined when a result is a NaN. The core generates NaNs with the

sign bit set to 1 (that is, negative). Also, infinity and zero are signed. Where possible, the sign is handled

in the same way as finite non-zero numbers. For example, , and

. A meaningless operation such as raises an invalid operation exception and

produces a NaN as a result.

X-Ref Target - Figure 2

Figure 2: Bit Fields within the Floating-Point Representation

Table 1: Special Values

Symbol for Special

Value

s Field e Field f Field

NaN don’t care -1 (that is, )

Any non-zero field.

For results that are NaN the

most significant bit of fraction is

set (that is, )

sign of -1 (that is, ) Zero (that is, )

sign of 0 Zero (that is, )

denormalized sign of number 0 Any non-zero field

fes

-1

-2w

-1w -1

-1

Bit position

Bit significance (i)

DS335_02_050609

b

1–

–=

i0=

1–



Ee2

1–

1––=



e 11...11=

f 10...00=





e 11...11=

f 00...00=

0

f 00...00=

0–0–+0–=

0–0+0=

– –+ –=

– +

LogiCORE IP Floating-Point Operator v5.0

4 www.xilinx.com DS335 March 1, 2011

Product Specification

IEEE-754 Support

The Xilinx Floating-Point core complies with much of the IEEE-754 Standard. The deviations generally

provide a better trade-off of resources against functionality. Specifically, the core deviates in the

following ways:

• Non-Standard Wordlengths

• Denormalized Numbers

• Rounding Modes

• Signaling and Quiet NaNs

Non-Standard Wordlengths

The Xilinx Floating-Point core supports a greater range of fraction and exponent wordlength than

defined in the IEEE-754 Standard.

Standard formats commonly implemented by programmable processors:

• Single Format – uses 32 bits, with a 24-bit fraction and 8-bit exponent.

• Double Format – uses 64 bits, with 53-bit fraction and 11-bit exponent.

Less commonly implemented standard formats are:

• Single Extended – wordlength extensions of 43 bits and above

• Double Extended – wordlength extensions of 79 bits and above

The Xilinx core supports formats with fraction and exponent wordlengths outside of these standard

wordlengths.

Denormalized Numbers

The exponent limits the size of numbers that may be represented. It is possible to extend the range for

small numbers using the minimum exponent value (0) and allowing the fraction to become

denormalized. That is, the hidden bit becomes zero such that . Now the value is

given by:

These denormalized numbers are extremely small. For example, with single precision the value is

bounded . As such, in most practical calculation they do not contribute to the end result.

Furthermore, as the denormalized value becomes smaller, it is represented with fewer bits and the

relative rounding error introduced by each operation is increased.

The Xilinx Floating-Point core does not support denormalized numbers. In FPGAs, the dynamic range

can be increased using fewer resources by increasing the size of the exponent (and a 1-bit increase for

single precision increases the range by ). If necessary, the overall wordlength of the format can be

maintained by an associated decrease in the wordlength of the fraction.

To provide robustness, the core treats denormalized operands as zero with a sign taken from the

denormalized number. Results that would have been denormalized are set to an appropriately signed

zero.

b

p1–

1

v1–

1–

2–





–

0.b

b

1–

126–



256

DS335 March 1, 2011 www.xilinx.com 5

Product Specification

LogiCORE IP Floating-Point Operator v5.0

The support for denormalized numbers cannot be switched off on some processors. Therefore, there

may be very small differences between values generated by the Floating-Point core and a program

running on a conventional processor when numbers are very small. If such differences must be

avoided, the arithmetic model on the conventional processor should include a simple check for

denormalized numbers. This check should set the output of an operation to zero when denormalized

numbers are detected to correctly reflect what happens in the FPGA implementation.

Rounding Modes

Only the default rounding mode, Round to Nearest (as defined by the IEEE-754 Standard), is currently

supported.

Signaling and Quiet NaNs

The IEEE-754 Standard requires provision of Signaling and Quiet NaNs. However, the Xilinx

Floating-Point core treats all NaNs as Quiet NaNs. When any NaN is supplied as one of the operands

to the core, the result is a Quiet NaN, and an invalid operation exception will not be raised (as would

be the case for signaling NaNs). The exception to this rule is floating-point to fixed-point conversion.

For detailed information, see the behavior of INVALID_OP.

Fixed-Point Number Representation

For the purposes of fixed-point to floating-point conversion, a fixed-point representation is adopted

that is consistent with the signed integer type used by Xilinx System Generator for DSP. Fixed-point

values are represented using a two’s complement number that is weighted by a fixed power of 2. The

binary representation of a fixed-point number contains three fields as shown in Figure 3 (although it is

still simply a weighted two’s complement number).

In Figure 3, the bit position has been labeled with an index i. Based upon this, the value of a fixed-point

number is given by:

For example, a 32-bit signed integer representation is obtained when a total width of 32 and a fraction

width of 0 are specified. Round to Nearest is employed within the conversion operations.

To provide for the sign bit, the width of the integer field must be at least 1, requiring that the fractional

width be no larger than w-1.

X-Ref Target - Figure 3

Figure 3: Bit Fields within the Fixed-Point Representation

fractionintegers

-1w

w -1

-1

Bit position (i)

DS335_03_050609

v1–

w1–w

–

w2–

b

1–

b

1–

w1–

w1–w

–

w2–



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