fpga axi-can ip核数据手册

DS791 June 22, 2011 www.xilinx.com 1

Product Specification

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Introduction

The Xilinx® LogiCORE™ IP Controller Area Network

(CAN) product specification defines the architecture

• Conforms to the ISO 11898 -1, CAN 2.0A, and CAN

• Supports both standard (11-bit identifier) and

extended (29-bit identifier) frames

• Supports bit rates up to 1 Mb/s

• Transmit message FIFO with a user-configurable

depth of up to 64 messages

• Sleep Mode with automatic walk-up

• Maskable Error and Status Interrupts

Virtex-6

Supported User

Interfaces

Model

Design Entry

Tools

XPS 13.2

Simulation

Mentor Graphics ModelSim

Synthesis Tools XST 13.2

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Product Specification

Figure 1 illustrates the high-level architecture of the CAN core. The CAN core requires an external 3.3 V compatible

Table 6 defines the configuration registers. This module allows for read and write access to the registers through the

Acceptance Filters sort incoming messages with the user-defined acceptance mask and ID registers to determine

whether to store messages in the RX FIFO, or to acknowledge and discard them. The number of acceptance filters

can be configured from 0 to 4. Messages passed through acceptance filters are stored in the RX FIFO.

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Product Specification

These bit time parts are comprised of a number of smaller segments of equal length called time quanta (tq). The

passed to the BTL module through the Baud Rate Prescaler (BRPR) register.

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Product Specification

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Product Specification

The AXI CAN I/O signals are listed and described inTable 1

P8 S_AXI_WVALID AXI I N/A

P9 S_AXI_WREADY AXI O 0x0