################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
vivado CORDIC 测试arctan功能工程 （119个子文件） 
__synthesis_is_complete__ 0B runme.bat 229B top_atan.dcp 2.75MB compile.do 2KB compile.do 2KB compile.do 2KB simulate.do 508B simulate.do 498B simulate.do 498B elaborate.do 373B compile.do 260B simulate.do 199B wave.do 12B wave.do 12B wave.do 12B wave.do 12B simulate.do 11B run.f 1KB run.f 1KB modelsim.ini 116KB xsim.ini 26KB vivado.jou 784B ISEWrap.js 8KB rundef.js 1KB runme.log 52KB atan.lpr 290B elab.opt 385B vivado.pb 77KB top_atan_utilization_synth.pb 224B vhdl.prj 106B top_atan_utilization_synth.rpt 7KB .vivado.begin.rst 219B .vivado.end.rst 0B .Vivado_Synthesis.queue.rst 0B cordic_atan.sh 8KB cordic_atan.sh 6KB cordic_atan.sh 6KB cordic_atan.sh 6KB cordic_atan.sh 5KB cordic_atan.sh 5KB cordic_atan.sh 5KB cordic_atan.sh 5KB ISEWrap.sh 2KB runme.sh 1KB top_atan.tcl 3KB cmd.tcl 464B
cordic_v6_0_changelog.txt 7KB README.txt 3KB README.txt 2KB README.txt 2KB README.txt 2KB README.txt 2KB README.txt 2KB README.txt 2KB README.txt 2KB README.txt 2KB file_info.txt 1KB file_info.txt 1KB file_info.txt 1KB file_info.txt 1KB file_info.txt 1KB file_info.txt 1KB htr.txt 393B README.txt 130B file_info.txt 105B file_info.txt 105B cordic_atan.udo 0B cordic_atan.udo 0B cordic_atan.udo 0B cordic_atan.udo 0B tb_atan.v 1KB top_atan.v 882B top_atan.vds 52KB cordic_atan.veo 3KB cordic_atan.veo 3KB mult_gen_v12_0_vh_rfs.vhd 1.25MB mult_gen_v12_0_vh_rfs.vhd 1.25MB cordic_v6_0_vh_rfs.vhd 575KB cordic_v6_0_vh_rfs.vhd 575KB c_addsub_v12_0_vh_rfs.vhd 395KB c_addsub_v12_0_vh_rfs.vhd 395KB axi_utils_v2_0_vh_rfs.vhd 286KB axi_utils_v2_0_vh_rfs.vhd 286KB xbip_utils_v3_0_vh_rfs.vhd 180KB xbip_utils_v3_0_vh_rfs.vhd 180KB xbip_dsp48_wrapper_v3_0_vh_rfs.vhd 180KB xbip_dsp48_wrapper_v3_0_vh_rfs.vhd 180KB xbip_bram18k_v3_0_vh_rfs.vhd 102KB xbip_bram18k_v3_0_vh_rfs.vhd 102KB xbip_dsp48_addsub_v3_0_vh_rfs.vhd 98KB xbip_dsp48_addsub_v3_0_vh_rfs.vhd 98KB c_reg_fd_v12_0_vh_rfs.vhd 39KB c_reg_fd_v12_0_vh_rfs.vhd 39KB xbip_addsub_v3_0_vh_rfs.vhd 34KB xbip_addsub_v3_0_vh_rfs.vhd 34KB xbip_pipe_v3_0_vh_rfs.vhd 30KB xbip_pipe_v3_0_vh_rfs.vhd 30KB tb_cordic_atan.vhd 16KB cordic_atan.vhd 9KB cordic_atan.vhd 8KB共 119 条
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