JEDEC
STANDARD
Power and Temperature Cycling
JESD22-A105D
(Revision of JESD22-A105C, January 2004, Reaffirmed January 2011)
JANUARY 2020
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and
approved through the JEDEC Board of Directors level and subsequently reviewed and approved
by the JEDEC legal counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum
delay the proper product for use by those other than JEDEC members, whether the standard is to
be used either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption
may involve patents or articles, materials, or processes. By such action JEDEC does not assume
any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
the JEDEC standards or publications.
The information included in JEDEC standards and publications represents a sound approach to
product specification and application, principally from the solid state device manufacturer
viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or
publication may be further processed and ultimately become an ANSI standard.
No claims to be in conformance with this standard may be made unless all requirements stated in
the standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication
should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards
and Documents for alternative contact information.
Published by
©JEDEC Solid State Technology Association 2020
3103 North 10th Street
Suite 240 South
Arlington, VA 22201-2107
This document may be downloaded free of charge; however JEDEC retains the
copyright on this material. By downloading this file the individual agrees not to
charge for or resell the resulting material.
PRICE: Contact JEDEC
Printed in the U.S.A.
All rights reserved
JEDEC Standard No. 22-A105D
Page 1
Test Method A105D
(Revision of A105C)
TEST METHOD A105D
POWER AND TEMPERATURE CYCLING
(From JEDEC Board Ballot JCB-19-24, formulated under the cognizance of the JC-14.1
Subcommittee on Reliability Test Methods for Packaged Devices.)
1 Scope
This test method applies to semiconductor devices that are subjected to temperature
excursions and required to power on and off during all temperatures. The power and
temperature cycling test is performed to determine the ability of a device to withstand
alternate exposures at high and low temperature extremes with operating biases
periodically applied and removed. It is intended to simulate worst case conditions
encountered in typical applications.
The power and temperature cycling test is considered destructive. It is intended for
device qualification.
2 Terms and definitions
2.1 Temperature cycle time
Time between one high temperature extreme to the next, or from one low temperature
extreme to the next, for a given sample; see Figure 1.
2.2 Ramp rate
The rate of temperature increase or decrease per unit of time for the sample(s). Ramp
rate should be measured for the linear portion of the profile curve, which is generally the range
between 10% and 90% of the test condition temperature range; see Figure 1. Note:
Ramp rate can be load dependent and should be verified for the load being tested.
2.3 Dwell time
The amount of time the sample temperature has exceeded the specified temperature,
either the high or the low temperature; see Figure 1.
2.4 Power cycle time
Time between one power on to the next, or from one power off to the next, for a given
sample; see Figure 1.
