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AD6642 AD6657评估板用户指南
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AD6642 AD6657评估板用户指南
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Evaluation Board User Guide
UG-232
One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Te l: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the AD6642/AD6657 Analog-to-Digital Converters
Please see the last page for an important warning and disclaimers. Rev. 0 | Page 1 of 32
FEATURES
Full featured evaluation board for the AD6642/AD6657
SPI interface for setup and control
External, on-board oscillator or AD9517 clocking options
Balun/transformer or amplifier input drive options
LDO regulator power supply
VisualAnalog® and SPI controller software interfaces
EQUIPMENT NEEDED
Analog signal source and antialiasing filter
Sample clock source (if not using the on-board oscillator)
2 switching power supplies (6.0 V, 2.5 A), CUI, Inc.
EPS060250UH-PHP-SZ, provided
PC running Windows® 98 (2nd ed.), Windows 2000,
Windows ME, or Windows XP
USB 2.0 port, recommended (USB 1.1 compatible)
AD6642 or AD6657 evaluation board
HSC-ADC-EVALCZ FPGA-based data capture kit
SOFTWARE NEEDED
VisualAnalog
SPI controller
DOCUMENTS NEEDED
AD6642 or AD6657 data sheet
HSC-ADC-EVALCZ data sheet
AN-905 Application Note, VisualAnalog Converter Evaluation
Tool, Version 1.0 User Manual
AN-878 Application Note, High Speed ADC SPI Control Software
AN-877 Application Note, Interfacing to High Speed ADCs via SPI
AN-835 Application Note, Understanding ADC Testing and
Evaluation
GENERAL DESCRIPTION
This document describes the AD6642 and AD6657 evaluation
board, which provides all of the support circuitry required to
operate the AD6642 or AD6657 in their various modes and
configurations. The application software used to interface with
the devices is also described.
The AD6642 and AD6657 data sheets provide additional
information and should be consulted when using the evaluation
board. All documents and software tools are available at
www.analog.com/fifo. For additional information or questions,
send an email to highspeed.converters@analog.com.
TYPICAL MEASUREMENT SETUP
09572-001
Figure 1. AD6642 and AD6657 Evaluation Board and HSC-ADC-EVALCZ Data Capture Board
UG-232 Evaluation Board User Guide
Rev. 0 | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Equipment Needed ........................................................................... 1
Software Needed ............................................................................... 1
Documents Needed .......................................................................... 1
General Description ......................................................................... 1
Typical Measurement Setup ............................................................ 1
Revision History ............................................................................... 2
Evaluation Board Hardware ............................................................ 3
Power Supplies .............................................................................. 3
Input Signals...................................................................................3
Output Signals ...............................................................................3
Default Operation and Jumper Selection Settings ....................5
Evaluation Board Software Quick Start Procedures .....................6
Configuring the Board .................................................................6
Using the Software for Testing .....................................................6
Evaluation Board Schematics and Artwork ................................ 11
Ordering Information .................................................................... 25
Bill of Materials ........................................................................... 25
REVISION HISTORY
12/10—Revision 0: Initial Version
Evaluation Board User Guide UG-232
Rev. 0 | Page 3 of 32
EVALUATION BOARD HARDWARE
The AD6642 and AD6657 evaluation board provides all of the
support circuitry required to operate these parts in their various
modes and configurations. Figure 2 shows the typical bench
characterization setup used to evaluate the ac performance of
the AD6642 or AD6657. It is critical that the signal sources used
for the analog input and clock have very low phase noise (<1 ps
rms jitter) to realize the optimum performance of the signal
chain. Proper filtering of the analog input signal to remove
harmonics and lower the integrated or broadband noise at the
input is necessary to achieve the specified noise performance.
The AD6642 and AD6657 evaluation board covers two general
part families. The boards are populated slightly differently for
each family. The AD6642 is one part supported by this evaluation
board, and the AD6657 is the second part supported by this
evaluation board. The evaluation board supports quad-channel
operation for the AD6657 while supporting dual-channel
operation for the AD6642.
See the Evaluation Board Software Quick Start Procedures section
to get started, and see Figure 20 to Figure 36 for the complete
schematics and layout diagrams. These diagrams demonstrate
the routing and grounding techniques that should be applied at
the system level when designing application boards using these
converters.
POWER SUPPLIES
This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2 A maximum output. Connect
the supply to the rated 100 V ac to the 240 V ac wall outlet at
47 Hz to 63 Hz. The output from the supply is provided through
a 2.1 mm inner diameter jack that connects to the printed circuit
board (PCB) at P201. The 6 V supply is fused and conditioned
on the PCB before connecting to the low dropout linear regulators
(default configuration) that supply the proper bias to each of the
various sections on the board.
The evaluation board can be powered in a nondefault condition
using external bench power supplies. To do this, the E201, E202,
E204, E205, and E207 ferrite beads can be removed to disconnect
the outputs from the on-board LDOs. This enables the user to
bias each section of the board individually. Use P202 and P203
to connect a different supply for each section. A 1.8 V supply is
needed with a 1 A current capability for DUT_AVDD and
DRVDD; however, it is recommended that separate supplies
be used for both analog and digital domains. An additional
supply is also required to supply 1.8 V for digital support circuitry
on the board, DVDD. This should also have a 1 A current
capability and can be combined with DRVDD with little or no
degradation in performance. To operate the evaluation board
using the SPI and alternate clock options, a separate 3.3 V analog
supply is needed in addition to the other supplies. This 3.3 V supply,
or 3P3V_ANALOG, should have a 1 A current capability. This
3.3 V supply is also used to support optional input path amplifiers
(ADL5562) on Channel A and Channel B. An additional supply,
5V_SUPPORT, is used to bias the optional dual input path
amplifier (AD8376) on Channel C and Channel D. If used,
these supplies should each have 1 A current capability.
INPUT SIGNALS
When connecting the clock and analog source, use clean signal
generators with low phase noise, such as the Rohde & Schwarz SMA,
or HP 8644B signal generators or an equivalent. Use a 1 m shielded,
RG-58, 50 Ω coaxial cable for connecting to the evaluation board.
Enter the desired frequency and amplitude (see the Specifications
section in the data sheet of the respective part). When connecting
the analog input source, use of a multipole, narrow-band band-pass
filter with 50 Ω terminations is recommended. Analog Devices, Inc.,
uses TTE and K&L Microwave, Inc., band-pass filters. The filters
should be connected directly to the evaluation board.
If an external clock source is used, it should also be supplied
with a clean signal generator as previously specified. Typically,
most Analog Devices evaluation boards can accept ~2.8 V p-p or
13 dBm sine wave input for the clock.
OUTPUT SIGNALS
The default setup uses the Analog Devices high speed converter
evaluation platform (HSC-ADC-EVALCZ) for data capture.
The output signals from Channel A/Channel B for the AD6642
and Channel A/Channel B/Channel C/Channel D for the AD6657
are routed through P951 and P952, respectively, to the FPGA on
the data capture board.
UG-232 Evaluation Board User Guide
Rev. 0 | Page 4 of 32
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
SWITCHING
POWER
SUPPLY
SWITCHING
POWER
SUPPLY
PC
RUNNING ADC
ANALYZER
OR VISUAL ANALOG
USER SOFTWARE
6V DC
2A MAX
6V DC
2A MAX
ANALOG FILTER
SIGNAL
SYNTHESIZER
SIGNAL
SYNTHESIZER
ANALOG FILTER
SIGNAL
SYNTHESIZER
ANALOG FILTER
ANALOG FILTER
SIGNAL
SYNTHESIZER
OPTIONAL CLOCK SOURCE
09572-002
Figure 2. Evaluation Board Connection
Evaluation Board User Guide UG-232
Rev. 0 | Page 5 of 32
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
This section explains the default and optional settings or modes
allowed on the AD6642/AD6657 Rev. B evaluation board.
Power Circuitry
Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P201.
Analog Input
The A and B channel inputs on the evaluation board are set up for
a double balun-coupled analog input with a 50 Ω impedance. This
input network is optimized to support a wide frequency band. See
the AD6642 and AD6657 data sheets for additional information on
the recommended networks for different input frequency ranges.
The nominal input drive level is 10 dBm to achieve 2 V p-p full
scale into 50 Ω. At higher input frequencies, slightly higher input
drive levels are required due to losses in the front-end network.
Optionally, Channel A and Channel B inputs on the board can
be configured to use the ADL5562 ultralow distortion RF/IF
differential amplifier. The ADL5562 components are included on
the evaluation board at U501 and U502. However, the path into
and out of the ADL5562 can be configured in many different ways
depending on the application; therefore, the parts in the input
and output path are left unpopulated. The user should see the
ADL5562 data sheet for additional information on this part and
for configuring the inputs and outputs. The ADL5562 by default
is held in power-down mode but can be enabled by adding a
jumper on P501 (Channel A) or P502 (Channel B). The ADL5562,
on the Channel A and Channel B inputs, can also be substituted
with the ADA4937 or the ADA4938 to allow evaluation of these
parts with the ADC.
The Channel C and Channel D inputs are set up with an optional
input path through the AD8376 digitally variable gain amplifier
(DVGA). Similar to Channel A and Channel B, the amplifier is
included on the board at U601; however, the input-/output-related
components are not included. The user should see the AD8376
data sheet for additional information on this part and for
configuring the inputs and outputs. The AD8376 channels are
also normally held in power-down mode and can be enabled by
adding a jumper on P602 (Channel C) or P601 (Channel D).
Clock Circuitry
The default clock input circuit that is populated on the
AD6642/AD6657 evaluation board uses a simple transformer-
coupled circuit using a high bandwidth 1:1 impedance ratio
transformer (T701) that adds a very low amount of jitter to the
clock path. The clock input is 50 Ω terminated and ac-coupled
to handle single-ended sine wave types of inputs. The transformer
converts the single-ended input to a differential signal that is
clipped by CR701 before entering the ADC clock inputs.
The board is set by default to use an external clock generator. An
external clock source capable of driving a 50 Ω terminated input
should be connected to J702.
A differential LVPECL clock driver output can also be used to
clock the ADC input using the AD9517 (U901). To place the
AD9517 into the clock path, populate R727 and R728 with 0 Ω
resistors and remove R713 and R714 to disconnect the default clock
path inputs. In addition, populate R817 and R816 with 0 Ω
resistors and remove R815 and R818 to disconnect the default
clock path outputs and insert the AD9517 LVPECL Output 1. The
AD9517 must be configured through the SPI controller software to
set up the PLL and other operation modes. Consult the AD9517
data sheet for more information about these and other options.
PDWN
To enable the power-down feature, add a shorting jumper across
P702 at Pin 1 and Pin 2 to connect the PDWN pin to AVDD.
NSR
To enable the noise shaping requantizer (NSR) feature, add a
shorting jumper across P701 at Pin 1 and Pin 2 to connect the
NSR ON pin to GND. The NSR feature can also be enabled via
the SPI interface by writing to Register 0x3C. Writing to Bit 4
allows the user to ignore the MODE pin and enable the NSR via
SPI control.
AD6642/AD6657
33Ω
0.1µF
2V p-p
VIN+
VIN–
VCM
8.2pF
8.2pF
33Ω
0.1µF
S
0.1µF
8.2pF
36Ω
36Ω
SP
A
P
49.9Ω
49.9Ω
09572-003
Figure 3. Default Analog Input Configuration of the AD6642/AD6657
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