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镁光 64M SDRAM 规格书
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SDR SDRAM
MT48LC16M4A2 – 4 Meg x 4 x 4 Banks
MT48LC8M8A2 – 2 Meg x 8 x 4 Banks
MT48LC4M16A2 – 1 Meg x 16 x 4 Banks
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full-page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh modes: standard and low-power
(not available on AT devices)
• Auto refresh
– 64ms, 4096-cycle refresh
(commercial and industrial)
– 16ms, 4096-cycle refresh
(automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
Options Marking
• Configuration
– 16 Meg x 4 (4 Meg x 4 x 4 banks) 16M4
3
– 8 Meg x 8 (2 Meg x 8 x 4 banks) 8M8
– 4 Meg x 16 (1 Meg x 16 x 4 banks) 4M16
• Write recovery (
t
WR)
–
t
WR = 2 CLK A2
• Plastic package – OCPL
1
– 54-pin TSOP II (400 mil) TG
– 54-pin TSOP II (400 mil) Pb-free P
– 54-ball VFBGA (x16 only) (8mm x
8mm)
F4
– 54-ball VFBGA (x16 only) (8mm x
8mm)
B4
2
• Timing – cycle time
– 6ns @ CL = 3 -6
3
– 6ns @ CL = 3 -6A
– 7.5ns @ CL = 3 (PC133) -75
3
– 7.5ns @ CL = 2 (PC133) -7E
• Self refresh
– Standard None
– Low-power L
3
• Operating temperature range
– Commercial (0˚C to +70˚C) None
– Industrial (–40˚C to +85˚C) IT
– Automotive (–40˚C to +105˚C) AT
2
• Revision :G, :J
Notes:
1. Off-center parting line.
2. Contact Micron for availability.
3. Available only on Revision G.
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
Clock
Frequency (MHz) Target
t
RCD-
t
RP-CL
t
RCD (ns)
t
RP (ns) CL (ns)
-6 167 3-3-3 18 18 18
-6A 167 3-3-3 18 18 18
-75 133 3-3-3 20 20 20
-7E 133 2-2-2 15 15 15
64Mb: x4, x8, x16 SDRAM
Features
PDF: 09005aef80725c0b
64mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Table 2: Address Table
Parameter 16 Meg x 4 8 Meg x 8 4 Meg x 16
Configuration 4 Meg x 4 x 4 banks 2 Meg x 8 x 4 banks 1 Meg x 16 x 4 banks
Refresh count 4K 4K 4K
Row addressing 4K A[11:0] 4K A[11:0] 4K A[11:0]
Bank addressing 4 BA[1:0] 4 BA[1:0] 4 BA[1:0]
Column addressing 1K A[9:0] 512 A[8:0] 256 A[7:0]
Table 3: 64Mb SDR Part Numbering
Part Numbers Architecture Package
MT48LC16M4A2TG 16 Meg x 4 54-pin TSOP II
MT48LC16M4A2P 16 Meg x 4 54-pin TSOP II
MT48LC8M8A2TG 8 Meg x 8 54-pin TSOP II
MT48LC8M8A2P 8 Meg x 8 54-pin TSOP II
MT48LC4M16A2TG 4 Meg x 16 54-pin TSOP II
MT48LC4M16A2P 4 Meg x 16 54-pin TSOP II
MT48LC4M16A2B4
1
4 Meg x 16 54-ball VFBGA
MT48LC4M16A2F4
1
4 Meg x 16 54-ball VFBGA
Note:
1. FBGA Device Decoder: www.micron.com/decoder.
64Mb: x4, x8, x16 SDRAM
Features
PDF: 09005aef80725c0b
64mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 1999 Micron Technology, Inc. All rights reserved.
Contents
General Description ......................................................................................................................................... 7
Automotive Temperature .............................................................................................................................. 7
Functional Block Diagrams ............................................................................................................................... 8
Pin and Ball Assignments and Descriptions ..................................................................................................... 11
Package Dimensions ....................................................................................................................................... 14
Temperature and Thermal Impedance ............................................................................................................ 16
Electrical Specifications .................................................................................................................................. 19
Electrical Specifications – I
DD
Parameters ........................................................................................................ 21
Electrical Specifications – AC Operating Conditions ......................................................................................... 23
Functional Description ................................................................................................................................... 27
Commands .................................................................................................................................................... 28
COMMAND INHIBIT .................................................................................................................................. 28
NO OPERATION (NOP) ............................................................................................................................... 29
LOAD MODE REGISTER (LMR) ................................................................................................................... 29
ACTIVE ...................................................................................................................................................... 29
READ ......................................................................................................................................................... 30
WRITE ....................................................................................................................................................... 31
PRECHARGE .............................................................................................................................................. 32
BURST TERMINATE ................................................................................................................................... 32
REFRESH ................................................................................................................................................... 33
AUTO REFRESH ..................................................................................................................................... 33
SELF REFRESH ....................................................................................................................................... 33
Truth Tables ................................................................................................................................................... 34
Initialization .................................................................................................................................................. 39
Mode Register ................................................................................................................................................ 41
Burst Length .............................................................................................................................................. 43
Burst Type .................................................................................................................................................. 43
CAS Latency ............................................................................................................................................... 45
Operating Mode ......................................................................................................................................... 45
Write Burst Mode ....................................................................................................................................... 45
Bank/Row Activation ...................................................................................................................................... 46
READ Operation ............................................................................................................................................. 47
WRITE Operation ........................................................................................................................................... 56
Burst Read/Single Write .............................................................................................................................. 63
PRECHARGE Operation .................................................................................................................................. 64
Auto Precharge ........................................................................................................................................... 64
AUTO REFRESH Operation ............................................................................................................................. 76
SELF REFRESH Operation ............................................................................................................................... 78
Power-Down .................................................................................................................................................. 80
Clock Suspend ............................................................................................................................................... 81
64Mb: x4, x8, x16 SDRAM
Features
PDF: 09005aef80725c0b
64mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 1999 Micron Technology, Inc. All rights reserved.
List of Figures
Figure 1: 16 Meg x 4 Functional Block Diagram ................................................................................................. 8
Figure 2: 8 Meg x 8 Functional Block Diagram ................................................................................................... 9
Figure 3: 4 Meg x 16 Functional Block Diagram ............................................................................................... 10
Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 11
Figure 5: 54-Ball VFBGA x16 (Top View) ......................................................................................................... 12
Figure 6: 54-Pin Plastic TSOP (400 mil) – Package Codes TG/P ......................................................................... 14
Figure 7: 54-Ball VFBGA (8mm x 8mm) – Package Codes F4/B4 ....................................................................... 15
Figure 8: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 17
Figure 9: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) .............................................. 18
Figure 10: ACTIVE Command ........................................................................................................................ 29
Figure 11: READ Command ........................................................................................................................... 30
Figure 12: WRITE Command ......................................................................................................................... 31
Figure 13: PRECHARGE Command ................................................................................................................ 32
Figure 14: Initialize and Load Mode Register .................................................................................................. 40
Figure 15: Mode Register Definition ............................................................................................................... 42
Figure 16: CAS Latency .................................................................................................................................. 45
Figure 17: Example: Meeting
t
RCD (MIN) When 2 <
t
RCD (MIN)/
t
CK
< 3 .......................................................... 46
Figure 18: Consecutive READ Bursts .............................................................................................................. 48
Figure 19: Random READ Accesses ................................................................................................................ 49
Figure 20: READ-to-WRITE ............................................................................................................................ 50
Figure 21: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 51
Figure 22: READ-to-PRECHARGE .................................................................................................................. 51
Figure 23: Terminating a READ Burst ............................................................................................................. 52
Figure 24: Alternating Bank Read Accesses ..................................................................................................... 53
Figure 25: READ Continuous Page Burst ......................................................................................................... 54
Figure 26: READ – DQM Operation ................................................................................................................ 55
Figure 27: WRITE Burst ................................................................................................................................. 56
Figure 28: WRITE-to-WRITE .......................................................................................................................... 57
Figure 29: Random WRITE Cycles .................................................................................................................. 58
Figure 30: WRITE-to-READ ............................................................................................................................ 58
Figure 31: WRITE-to-PRECHARGE ................................................................................................................. 59
Figure 32: Terminating a WRITE Burst ............................................................................................................ 60
Figure 33: Alternating Bank Write Accesses ..................................................................................................... 61
Figure 34: WRITE – Continuous Page Burst ..................................................................................................... 62
Figure 35: WRITE – DQM Operation ............................................................................................................... 63
Figure 36: READ With Auto Precharge Interrupted by a READ ......................................................................... 65
Figure 37: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 66
Figure 38: READ With Auto Precharge ............................................................................................................ 67
Figure 39: READ Without Auto Precharge ....................................................................................................... 68
Figure 40: Single READ With Auto Precharge .................................................................................................. 69
Figure 41: Single READ Without Auto Precharge ............................................................................................. 70
Figure 42: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 71
Figure 43: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 71
Figure 44: WRITE With Auto Precharge ........................................................................................................... 72
Figure 45: WRITE Without Auto Precharge ..................................................................................................... 73
Figure 46: Single WRITE With Auto Precharge ................................................................................................. 74
Figure 47: Single WRITE Without Auto Precharge ............................................................................................ 75
Figure 48: Auto Refresh Mode ........................................................................................................................ 77
Figure 49: Self Refresh Mode .......................................................................................................................... 79
Figure 50: Power-Down Mode ........................................................................................................................ 80
64Mb: x4, x8, x16 SDRAM
Features
PDF: 09005aef80725c0b
64mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 1999 Micron Technology, Inc. All rights reserved.
Figure 51: Clock Suspend During WRITE Burst ............................................................................................... 81
Figure 52: Clock Suspend During READ Burst ................................................................................................. 82
Figure 53: Clock Suspend Mode ..................................................................................................................... 83
64Mb: x4, x8, x16 SDRAM
Features
PDF: 09005aef80725c0b
64mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 1999 Micron Technology, Inc. All rights reserved.
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