LPDDR6 Specification PROPOSED Item# 1891.99
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4.2.2.2.1.1 ZQ Resistor Sharing in Background Calibration Mode ............................................................ 73
4.2.2.2.2 Stopping Background Calibration when DVFSQ is active ....................................................... 73
4.2.2.2.3 Stopping Background Calibration when VDDQ is Powered Off ............................................... 74
4.2.2.2.4 Stopping Background Calibration during VDD2C is ramping up or do .................................... 74
4.2.2.2.5 Stopping Background Calibration during VDD2D is ramping up or down ............................... 74
4.2.2.3 ZQ Reset .................................................................................................................................. 75
4.2.2.4 Multi-die Package Considerations ........................................................................................... 75
4.2.2.4.1 Other Considerations in Background Calibration Mode ........................................................... 76
4.2.2.5 ZQ External Resistor, Tolerance, and Capacitive Loading ...................................................... 76
4.2.2.6 Flow Chart Examples ............................................................................................................... 76
4.2.2.7 Flow Chart Examples ............................................................................................................... 77
4.2.3 LPDDR6 Command Bus Training (CBT) .................................................................................. 80
4.2.3.1 Introduction .............................................................................................................................. 80
4.2.3.1.1 Entry and Exit for CBT Mode ................................................................................................... 80
4.2.3.1.1.1 Entering CBT Mode .................................................................................................................. 81
4.2.3.1.1.2 Exiting CBT Mode .................................................................................................................... 81
4.2.3.1.2 Frequency Set Point (FSP) and Frequency Switching ............................................................ 81
4.2.3.1.3 VREF CA and DQ Bus Input/Output Control During CBT Mode .............................................. 82
4.2.3.1.4 CK Sync OFF and LFSR Reset ............................................................................................... 82
4.2.3.1.5 Data bit (DQ) function during CBT ........................................................................................... 83
4.2.3.1.6 Mapping of CA Input pins to DQ output Pins ........................................................................... 83
4.2.3.1.7 PRBS generator for CBT.......................................................................................................... 84
4.2.3.1.8 Command Bus Training sequence ........................................................................................... 85
4.2.3.1.9 Training Sequence steps for Single-Rank Systems................................................................. 86
4.2.3.1.10 Training Sequence steps Multi-Rank Systems ........................................................................ 87
4.2.4 CA VREF Training .................................................................................................................... 93
4.2.5 DQ VREF Training ................................................................................................................... 93
4.2.6 CS VREF Training .................................................................................................................... 93
4.2.7 WCK2CK Leveling ................................................................................................................... 94
4.2.7.1 WCK2CK Leveling Mode ......................................................................................................... 94
4.2.7.2 WCK2CK Leveling Procedure and Related AC Parameters .................................................... 95
4.2.8 Duty Cycle Adjuster (DCA) ...................................................................................................... 98
4.2.8.1 Duty Cycle Adjuster Range ...................................................................................................... 98
4.2.8.2 Relationship between WCK waveform and DCA Code Change .............................................. 99
4.2.8.3 The relationship between DCA Code Change and DQ output/RDQS timing ........................ 100
4.2.9 Read DCA (Duty Cycle Adjuster) .......................................................................................... 101
4.2.9.1 Read Duty Cycle Adjuster Range .......................................................................................... 101
4.2.9.2 The relationship between Read DCA Code Change and DQ output/RDQS timing ............... 101
4.2.10 Duty Cycle Monitor (DCM) ..................................................................................................... 102
4.2.10.1 DCM Functional Description .................................................................................................. 102
4.2.10.2 DCM Sequence ...................................................................................................................... 102
4.2.11 READ DQ Calibration ............................................................................................................. 104
4.2.11.1 READ DQ Calibration Training Procedure ............................................................................. 104
4.2.11.2 READ DQ Calibration Example ............................................................................................. 106
4.2.11.3 READ DQ Calibration after Power Down Exit ........................................................................ 107
4.2.12 WCK-DQ Training .................................................................................................................. 108
4.2.12.1 Training Procedure ................................................................................................................. 108
4.2.12.1.1 WCK to DQ Training Requirement ......................................................................................... 109
4.2.12.1.2 Packet Format for WCK to DQ Training ................................................................................. 110
4.2.12.1.3 Relationship between MR Setting and FIFO Training Behavior ............................................ 111
4.2.12.2 FIFO Pointer Reset and Synchronism ................................................................................... 111
4.2.12.3 Timing Diagrams .................................................................................................................... 112
4.2.12.4 Command Constraints for Write/Read FIFO Command ........................................................ 114
4.2.13 Enhanced RDQS Training ...................................................................................................... 116
4.2.14 RDQS Toggle Mode ............................................................................................................... 119
4.2.15 Rx Offset Calibration Training ................................................................................................ 121
4.2.15.1 Offset Calibration Training Description .................................................................................. 121
4.2.15.2 Offset Calibration Training Sequence .................................................................................... 121
