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LPDDR6规范提案及偏移校准训练序列
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2024-10-25
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内容概要:本文档主要介绍了拟议中的LPDDR6规范及其关键特性,尤其是偏移校准训练序列(Offset Calibration Training Sequence)。文中详细描述了如何进行CAS命令的操作以及模式寄存器写入(MRW)命令用于启动和退出偏移校准训练的具体步骤。此外,还探讨了动态效率模式(Dynamic Efficiency Mode),在此模式下可以通过减少数据带宽来节省功耗。 适合人群:内存设计与开发工程师、半导体技术研究人员、系统架构师。 使用场景及目标:适用于希望了解最新LPDDR6规范和技术特性的专业技术人员。主要用于提高内存系统的性能和能效比,同时降低功耗。 其他说明:本文档由JEDEC固态技术协会发布,详细记录了委员会对新规范的更新和批准情况,提供了重要的技术支持和指导。
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3103 NORTH 10
TH
STREET, SUITE 240-S, ARLINGTON, VA 22201, USA | PH +1.703.907.7540 | FX +1.703.907.7583 | WWW.JEDEC.ORG
Solid State Technology Association
COMMITTEE LETTER BALLOT
JEDEC Confidential Document
COMMITTEE: JC-42.6
ITEM NUMBER: 1891.99
DATE: 2024-10-7
SUBJECT: Proposed LPDDR6 Specification
BACKGROUND: Reference:
tg426_9^20240515^1891.99^Micron^LPDDR6_Specification.pdf
(https://www.jedec.org/members/documents/97473/download)
The committee approved to issue committee fast track ballot and
BOD ballot on October 2
nd
interim sub-committee meeting include
following updates.
The definitions which are approved by committee/TG on October 2,
2024, were added/replaced to 241007 editions.
Page that is modified is indicated green side bar and reference
material ID is described on the bottom on each page.
The definitions which are approved by committee and/or TG until
September 25, 2024, were added/replaced to 240928 editions.
Page that is modified is indicated magenta side bar and reference
material ID is described on the bottom on each page.
KEYWORDS: LPDDR6, Specification
SPONSOR:
ORIGINATOR:
Osamu Nagashima
Osamu Nagashima
Shunichi Saito
Micron
Micron
onagashima@micron.com
onagashima@micron.com
shsaito@micron.com
3103 NORTH 10
TH
STREET, SUITE 240-S, ARLINGTON, VA 22201, USA | PH +1.703.907.7540 | FX +1.703.907.7583 | WWW.JEDEC.ORG
Solid State Technology Association
COMMITTEE LETTER BALLOT
JEDEC Confidential Document
COMMITTEE: JC-42.6
ITEM NUMBER: 1891.99
DATE: 2024-10-7
SUBJECT: Proposed LPDDR6 Specification
BACKGROUND: Reference:
tg426_9^20240515^1891.99^Micron^LPDDR6_Specification.pdf
(https://www.jedec.org/members/documents/97473/download)
The definitions which are approved by committee/TG on October 2,
2024, were added/replaced to 241007 editions.
Page that is modified is indicated green side bar and reference
material ID is described on the bottom on each page.
The definitions which are approved by committee and/or TG until
September 25, 2024, were added/replaced to 240928 editions.
Page that is modified is indicated magenta side bar and reference
material ID is described on the bottom on each page.
KEYWORDS: LPDDR6, Specification
SPONSOR:
ORIGINATOR:
Osamu Nagashima
Osamu Nagashima
Shunichi Saito
Micron
Micron
onagashima@micron.com
onagashima@micron.com
shsaito@micron.com
LPDDR6 Specification PROPOSED Item# 1891.99
2
Contents
1 Scope ....................................................................................................................................... 26
2 Overview .................................................................................................................................. 27
2.1 Features ................................................................................................................................... 27
2.2 Functional Description.............................................................................................................. 27
2.2.1 Pad Definition and Description ................................................................................................. 29
2.2.1.1 Block Diagram .......................................................................................................................... 30
2.2.1.1.1 x24 mode configuration (Normal mode) ................................................................................... 30
2.2.1.1.2 x12 DQs Efficiency mode configuration ................................................................................... 31
2.2.2 LPDDR6 SDRAM Addressing .................................................................................................. 33
2.2.1 Speed Grade ............................................................................................................................ 35
2.2.2 Title-3 Data Packet Format ...................................................................................................... 36
2.2.2.1 The features related to the metadata contents ........................................................................ 36
2.2.2.2 Title-4 Data Packet Format ...................................................................................................... 36
2.2.3 Read Write burst chunk and Order .......................................................................................... 40
2.2.3.1 Read ......................................................................................................................................... 40
2.2.3.1.1 Data and Meta data .................................................................................................................. 40
2.2.3.1.2 Read burst chunk and sequence ............................................................................................. 40
2.2.3.1.2.1 Read BL24 operation: 32byte access ...................................................................................... 40
2.2.3.1.2.2 Read operation: 64byte access ............................................................................................... 42
2.2.3.2 Write ......................................................................................................................................... 45
2.2.3.2.1 Data and Meta data .................................................................................................................. 45
2.2.3.2.2 Write burst chunk and sequence ............................................................................................. 45
2.2.3.2.2.1 Write BL24 operation: 32byte access ...................................................................................... 45
2.2.3.2.2.2 Write operation: 64byte access ................................................................................................ 45
2.2.3.3 Burst Sequence ........................................................................................................................ 46
3 WCK Clocking .......................................................................................................................... 49
4 Initialization and Training.......................................................................................................... 53
4.1 Power-up, Initialization and Power-off Procedure .................................................................... 53
4.1.1 Voltage Ramp and Device Initialization .................................................................................... 53
4.1.2 Reset Initialization with Stable Power ...................................................................................... 56
4.1.3 Power-off Sequence ................................................................................................................. 57
4.2 Training .................................................................................................................................... 58
4.2.1 LPDDR6 CS Training ............................................................................................................... 58
4.2.1.1 Introduction .............................................................................................................................. 58
4.2.1.2 Entry and Exit for CS Training Mode ........................................................................................ 58
4.2.1.2.1 Entering CS Training Mode ...................................................................................................... 58
4.2.1.2.2 Exiting CS Training Mode......................................................................................................... 58
4.2.1.3 CS Training Mode (CSTM) Operation ...................................................................................... 59
4.2.1.4 Frequency Set Point (FSP) and Frequency Switching ............................................................ 59
4.2.1.5 VREF(CS) Update and DQ Bus Input/Output Control During CS Training mode ................... 60
4.2.1.6 Data bits (DQ) function during CSTM ...................................................................................... 61
4.2.1.7 CS Training Sequence Steps ................................................................................................... 61
4.2.1.8 CS-CK sweeping Cases........................................................................................................... 65
4.2.1.8.1 Case 0: CS-CK has 0 Skew (Ideal condition) .......................................................................... 65
4.2.1.8.2 Case 1: CS-CK has x Skew (CS is delayed by x) .................................................................... 65
4.2.1.8.3 Case 2: CS-CK has >1/2tCK Skew (CS is delayed by >1/2tCK) ............................................. 66
4.2.1.8.4 Case 3a: CS-CK marginally close (CS rising edge very close to CK rising edge) .................. 66
4.2.1.8.5 Case 3b: No CS high capture due to DCD on High PW .......................................................... 67
4.2.2 ZQ Calibration .......................................................................................................................... 69
4.2.2.1 Calibration During Powerup and Initialization .......................................................................... 69
4.2.2.1.1 Background Calibration ............................................................................................................ 70
4.2.2.1.2 Latching ZQ Calibration Results in Background Calibration Mode .......................................... 71
4.2.2.1.3 Maintaining Accurate Calibration - Background Calibration Mode .......................................... 72
4.2.2.2 ZQ Stop Functionality ............................................................................................................... 73
4.2.2.2.1 ZQ Resistor Sharing by Other Device(s) ................................................................................. 73
LPDDR6 Specification PROPOSED Item# 1891.99
3
4.2.2.2.1.1 ZQ Resistor Sharing in Background Calibration Mode ............................................................ 73
4.2.2.2.2 Stopping Background Calibration when DVFSQ is active ....................................................... 73
4.2.2.2.3 Stopping Background Calibration when VDDQ is Powered Off ............................................... 74
4.2.2.2.4 Stopping Background Calibration during VDD2C is ramping up or do .................................... 74
4.2.2.2.5 Stopping Background Calibration during VDD2D is ramping up or down ............................... 74
4.2.2.3 ZQ Reset .................................................................................................................................. 75
4.2.2.4 Multi-die Package Considerations ........................................................................................... 75
4.2.2.4.1 Other Considerations in Background Calibration Mode ........................................................... 76
4.2.2.5 ZQ External Resistor, Tolerance, and Capacitive Loading ...................................................... 76
4.2.2.6 Flow Chart Examples ............................................................................................................... 76
4.2.2.7 Flow Chart Examples ............................................................................................................... 77
4.2.3 LPDDR6 Command Bus Training (CBT) .................................................................................. 80
4.2.3.1 Introduction .............................................................................................................................. 80
4.2.3.1.1 Entry and Exit for CBT Mode ................................................................................................... 80
4.2.3.1.1.1 Entering CBT Mode .................................................................................................................. 81
4.2.3.1.1.2 Exiting CBT Mode .................................................................................................................... 81
4.2.3.1.2 Frequency Set Point (FSP) and Frequency Switching ............................................................ 81
4.2.3.1.3 VREF CA and DQ Bus Input/Output Control During CBT Mode .............................................. 82
4.2.3.1.4 CK Sync OFF and LFSR Reset ............................................................................................... 82
4.2.3.1.5 Data bit (DQ) function during CBT ........................................................................................... 83
4.2.3.1.6 Mapping of CA Input pins to DQ output Pins ........................................................................... 83
4.2.3.1.7 PRBS generator for CBT.......................................................................................................... 84
4.2.3.1.8 Command Bus Training sequence ........................................................................................... 85
4.2.3.1.9 Training Sequence steps for Single-Rank Systems................................................................. 86
4.2.3.1.10 Training Sequence steps Multi-Rank Systems ........................................................................ 87
4.2.4 CA VREF Training .................................................................................................................... 93
4.2.5 DQ VREF Training ................................................................................................................... 93
4.2.6 CS VREF Training .................................................................................................................... 93
4.2.7 WCK2CK Leveling ................................................................................................................... 94
4.2.7.1 WCK2CK Leveling Mode ......................................................................................................... 94
4.2.7.2 WCK2CK Leveling Procedure and Related AC Parameters .................................................... 95
4.2.8 Duty Cycle Adjuster (DCA) ...................................................................................................... 98
4.2.8.1 Duty Cycle Adjuster Range ...................................................................................................... 98
4.2.8.2 Relationship between WCK waveform and DCA Code Change .............................................. 99
4.2.8.3 The relationship between DCA Code Change and DQ output/RDQS timing ........................ 100
4.2.9 Read DCA (Duty Cycle Adjuster) .......................................................................................... 101
4.2.9.1 Read Duty Cycle Adjuster Range .......................................................................................... 101
4.2.9.2 The relationship between Read DCA Code Change and DQ output/RDQS timing ............... 101
4.2.10 Duty Cycle Monitor (DCM) ..................................................................................................... 102
4.2.10.1 DCM Functional Description .................................................................................................. 102
4.2.10.2 DCM Sequence ...................................................................................................................... 102
4.2.11 READ DQ Calibration ............................................................................................................. 104
4.2.11.1 READ DQ Calibration Training Procedure ............................................................................. 104
4.2.11.2 READ DQ Calibration Example ............................................................................................. 106
4.2.11.3 READ DQ Calibration after Power Down Exit ........................................................................ 107
4.2.12 WCK-DQ Training .................................................................................................................. 108
4.2.12.1 Training Procedure ................................................................................................................. 108
4.2.12.1.1 WCK to DQ Training Requirement ......................................................................................... 109
4.2.12.1.2 Packet Format for WCK to DQ Training ................................................................................. 110
4.2.12.1.3 Relationship between MR Setting and FIFO Training Behavior ............................................ 111
4.2.12.2 FIFO Pointer Reset and Synchronism ................................................................................... 111
4.2.12.3 Timing Diagrams .................................................................................................................... 112
4.2.12.4 Command Constraints for Write/Read FIFO Command ........................................................ 114
4.2.13 Enhanced RDQS Training ...................................................................................................... 116
4.2.14 RDQS Toggle Mode ............................................................................................................... 119
4.2.15 Rx Offset Calibration Training ................................................................................................ 121
4.2.15.1 Offset Calibration Training Description .................................................................................. 121
4.2.15.2 Offset Calibration Training Sequence .................................................................................... 121
LPDDR6 Specification PROPOSED Item# 1891.99
4
5 Simplified LPDDR6 State Diagram ........................................................................................ 122
6 Mode Register ........................................................................................................................ 127
6.1 Mode Register Definition ........................................................................................................ 128
6.1.1 Mode Register Definition ........................................................................................................ 133
7 Operating ............................................................................................................................... 215
7.1 Command Truth Tables .......................................................................................................... 216
7.2 Every other cycle command input .......................................................................................... 220
7.2.1 Command input ...................................................................................................................... 220
7.2.2 CK sync and sync off operation ............................................................................................. 220
7.2.2.1 CK sync off operation ............................................................................................................. 220
7.2.2.2 CK sync operation .................................................................................................................. 221
7.3 WCK Operation ...................................................................................................................... 223
7.3.1 WCK2CK Synchronization operation ..................................................................................... 223
7.3.1.1 WCK2CK Synchronization ..................................................................................................... 223
7.3.1.2 WCK2CK Synchronization Mode ........................................................................................... 223
7.3.1.3 WCK2CK training ................................................................................................................... 223
7.3.1.4 Auto-sync off mode ................................................................................................................ 224
7.3.1.4.1 Read with WCK2CK synchronization ..................................................................................... 224
7.3.1.4.2 Write with WCK2CK synchronization ..................................................................................... 228
7.3.1.4.3 CAS with WCK2CK synchronization ...................................................................................... 231
7.3.1.4.4 Rank to rank WCK2CK Sync operation ................................................................................. 234
7.3.1.4.5 WCK2CK SYNC Off Timing Definition ................................................................................... 237
7.3.1.5 Write Clock Always on mode (WCK Always on mode) ......................................................... 238
7.3.1.5.1 Sync-off command: CAS(WS_OFF=1) ................................................................................. 241
7.4 WCK2CK SYNC Off Timing Definition ................................................................................... 243
7.4.1 WCK Sync-Off Extension overview ........................................................................................ 247
7.4.1.1 WCK Sync-Off Extension functionality ................................................................................... 247
7.5 Row operation ........................................................................................................................ 249
7.5.1 Activate Command ................................................................................................................. 249
7.5.1.1 Sequential Bank Activation Restriction .................................................................................. 251
7.5.2 Pre-Charge Operation ............................................................................................................ 252
7.5.2.1 Pre-Charge Operation ............................................................................................................ 252
7.5.2.2 Auto-Precharge Operation ..................................................................................................... 254
7.5.2.2.1 Delay time from Write to Read with Auto Precharge ............................................................. 255
7.5.2.2.2 Burst Read with Auto-Precharge ............................................................................................ 256
7.5.2.2.3 Burst Write with Auto-Precharge ............................................................................................ 257
7.5.2.3 Read and Read-to-Precharge Latencies ............................................................................... 258
7.5.2.4 Write to Auto Precharge time ................................................................................................. 263
8 Read/Write Operation ............................................................................................................ 268
8.1 Read/Write Operations ........................................................................................................... 268
8.1.1 Read Operation ...................................................................................................................... 268
8.1.2 Read Preamble and Postamble ............................................................................................. 268
8.1.3 Burst Read Operation ............................................................................................................ 269
8.1.3.1 Read Timing ........................................................................................................................... 270
8.1.3.2 Read to Read Operation without additional WCK2CK-sync .................................................. 271
8.1.3.3 Read to Read Operation with additional WCK2CK-sync ....................................................... 273
8.1.3.4 Read operation followed by Write operation without additional WCK2CK-sync .................... 274
8.1.3.5 Read operation followed by Write operation with additional WCK2CK-sync ......................... 275
8.1.3.6 Read operation followed by Write operation on WCK Always On mode ............................... 276
8.1.4 RDQS Mode ........................................................................................................................... 277
8.1.4.1 RDQS Timing ......................................................................................................................... 277
8.1.4.2 RDQS Related Functionalities ............................................................................................... 278
8.1.4.3 RDQS Pre Shift ...................................................................................................................... 281
8.1.4.4 RDQS Half Rate toggle setting .............................................................................................. 285
8.1.4.5 RDQS Pattern Definition ........................................................................................................ 289
8.1.4.6 Mode Registers for RDQS ..................................................................................................... 290
8.1.5 Write Operation ...................................................................................................................... 291
8.1.6 Burst Write Operation ............................................................................................................. 291
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