AD5724芯片FPGAVerilog驱动源码+4通道12bit位宽的DAC芯片AD5724技术手册.zip资源-CSDN文库

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AD5724芯片FPGA Verilog驱动源码+4通道12bit位宽的DAC芯片AD5724技术手册.zip （16个子文件）

AD5754_evalSoftware

Setup.exe 55KB

data2.cab 3.01MB

ADI.ico 2KB

data1.hdr 65KB

autorun.inf 39B

setup.inx 132KB

layout.bin 453B

AD5754setup_rev1.8.exe 4.58MB

$PLUGINSDIR

GetVersion.dll 10KB

ADI_PDA_Drivers.exe 653KB

data1.cab 501KB

Setup.ini 129B

AD5754R.exe 164KB

ikernel.ex_ 338KB

ad5724_ctrl.v 10KB

AD5724.pdf 1.18MB

Complete, Quad, 12-/14-/16-Bit, Serial Input,

Unipolar/Bipolar Voltage Output DACs

AD5724/AD5734/AD5754

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Complete, quad, 12-/14-/16-bit digital-to-analog converter

(DAC)

Operates from single/dual supplies

Software programmable output range

+5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V

INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum

Total unadjusted error (TUE): 0.1% FSR maximum

Settling time: 10 μs typical

Integrated reference buffers

Output control during power-up/brownout

Simultaneous updating via

LDAC

Asynchronous

CLR

to zero scale or midscale

DSP-/microcontroller-compatible serial interface

24-lead TSSOP

Operating temperature range: −40°C to +85°C

iCMOS process technology

APPLICATIONS

Industrial automation

Closed-loop servo control, process control

Automotive test and measurement

Programmable logic controllers

GENERAL DESCRIPTION

The AD5724/AD5734/AD5754 are quad, 12-/14-/16-bit, serial

input, voltage output digital-to-analog converters. They operate

from single-supply voltages from +4.5 V up to +16.5 V or dual-

supply voltages from ±4.5 V up to ±16.5 V. Nominal full-scale

output range is software-selectable from +5 V, +10 V, +10.8 V,

±5 V, ±10 V, or ±10.8 V. Integrated output amplifiers, reference

buffers, and proprietary power-up/power-down control circuitry

are also provided.

The parts offer guaranteed monotonicity, integral nonlinearity

(INL) of ±16 LSB maximum, low noise, and 10 μs maximum

settling time.

The AD5724/AD5734/AD5754 use a serial interface that operates

at clock rates up to 30 MHz and are compatible with DSP and

microcontroller interface standards. Double buffering allows

the simultaneous updating of all DACs. The input coding is

user-selectable twos complement or offset binary for a bipolar

output (depending on the state of Pin BIN/

2sComp

), and straight

binary for a unipolar output. The asynchronous clear function

clears all DAC registers to a user-selectable zero-scale or midscale

output. The parts are available in a 24-lead TSSOP and offer

guaranteed specifications over the −40°C to +85°C industrial

temperature range.

FUNCTIONAL BLOCK DIAGRAM

6468-001

DAC C

DAC D

DAC B

INPUT

DAC A

LDAC

REFIN

OUT

REFERENCE BUFFERS

SDIN

SCLK

SYNC

SDO

CLR

GND

BIN/2sCOMP

DAC_GND (2) SIG_GND (2)

AD5724/AD5734/AD5754

INPUT SHIFT

AND

CONTROL

LOGIC

INPUT

DAC

AD5724: n = 12-BIT

AD5734: n = 14-BIT

AD5754: n = 16-BIT

Figure 1.

For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS® is a technology

platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and

package size, as well as increased ac and dc performance.

AD5724/AD5734/AD5754

Rev. 0 | Page 2 of 32

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3 

AC Performance Characteristics ................................................ 5

Timing Characteristics ................................................................ 5

Timing Diagrams .......................................................................... 6

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 16

Theory of Operation ...................................................................... 18

Architecture ................................................................................. 18

Serial Interface ............................................................................ 18

Load DAC (

LDAC

) ..................................................................... 20

Asynchronous Clear (

CLR

) ....................................................... 20

Configuring the AD5724/AD5734/AD5754 .......................... 20

Transfer Function ....................................................................... 20

Input Shift Register .................................................................... 24

DAC Register .............................................................................. 24

Output Range Select Register ................................................... 25

Control Register ......................................................................... 25

Power Control Register ............................................................. 26

Features ............................................................................................ 27

Analog Output Control ............................................................. 27

Power-Down Mode .................................................................... 27

Overcurrent Protection ............................................................. 27

Thermal Shutdown .................................................................... 27

Applications Information .............................................................. 28

+5 V/±5 V Operation ................................................................ 28

Layout Guidelines....................................................................... 28

Galvanically Isolated Interface ................................................. 28

Voltage Reference Selection ...................................................... 28

Microprocessor Interfacing ....................................................... 29

Outline Dimensions ....................................................................... 30

Ordering Guide .......................................................................... 30

REVISION HISTORY

8/08—Revision 0: Initial Version

AD5724/AD5734/AD5754

Rev. 0 | Page 3 of 32

SPECIFICATIONS

= 4.5 V

to 16.5 V; AV

= −4.5 V

to −16.5 V, or 0 V; GND = 0 V; REFIN= 2.5 V; DV

= 2.7 V to 5.5 V; R

LOAD

= 2 kΩ;

LOAD

= 200 pF; all specifications T

MIN

to T

MAX

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

ACCURACY Outputs unloaded

Resolution

AD5754 16 Bits

AD5734 14 Bits

AD5724 12 Bits

Total Unadjusted Error (TUE)

A Version −0.3 +0.3 % FSR

B Version −0.1 +0.1 % FSR

Relative Accuracy (INL)

AD5754 −16 +16 LSB

AD5734 −4 +4 LSB

AD5724 −1 +1 LSB

Differential Nonlinearity (DNL) −1 +1 LSB All models, all versions, guaranteed monotonic

Bipolar Zero Error −6 +6 mV

= 25°C, error at other temperatures obtained

using bipolar zero error TC

Bipolar Zero Error TC

±4 ppm FSR/°C

Zero-Scale Error −6 6 mV

= 25°C, error at other temperatures

obtained using zero-scale error TC

Zero-Scale Error TC

±4 ppm FSR/°C

Offset Error −6 +6 mV

= 25°C, error at other temperatures

obtained using offset error TC

Offset Error TC

±4 ppm FSR/°C

Gain Error −0.025 +0.025 % FSR

±10 V range, T

= 25°C, error at other

temperatures obtained using gain error TC

Gain Error

−0.065 0 % FSR

+10 V and +5 V ranges, T

= 25°C, error at other

temperatures obtained using gain error TC

Gain Error

0 +0.08 % FSR

±5 V range, T

= 25°C, error at other

temperatures obtained using gain error TC

Gain Error TC

±8 ppm FSR/°C

DC Crosstalk

120 μV

REFERENCE INPUT

Reference Input Voltage 2.5 V ±1% for specified performance

DC Input Impedance 1 5 MΩ

Input Current −2 ±0.5 +2 μA

Reference Range 2 3 V

OUTPUT CHARACTERISTICS

Output Voltage Range −10.8 +10.8 V AV

/AV

= ±11.7 V min, REFIN = +2.5 V

−12 +12 V AV

/AV

= ±12.9 V min, REFIN = +3 V

Headroom Required 0.5 0.9 V

Output Voltage TC ±4 ppm FSR/°C

Short-Circuit Current 20 mA

Load 2 kΩ For specified performance

Capacitive Load Stability 4000 pF

DC Output Impedance 0.5 Ω

AD5724/AD5734/AD5754

Rev. 0 | Page 4 of 32

Parameter Min Typ Max Unit Test Conditions/Comments

DIGITAL INPUTS

= 2.7 V to 5.5 V, JEDEC compliant

Input High Voltage, V

2 V

Input Low Voltage, V

0.8 V

Input Current ±1 μA Per pin

Pin Capacitance 5 pF Per pin

DIGITAL OUTPUTS (SDO)

Output Low Voltage, V

0.4 V DV

= 5 V ± 10%, sinking 200 μA

Output High Voltage, V

− 1 V DV

= 5 V ± 10%, sourcing 200 μA

Output Low Voltage, V

0.4 V DV

= 2.7 V to 3.6 V, sinking 200 μA

Output High Voltage, V

− 0.5 V DV

= 2.7 V to 3.6 V, sourcing 200 μA

High Impedance Leakage Current −1 +1 μA

High Impedance Output Capacitance 5 pF

POWER REQUIREMENTS

4.5 16.5 V

−4.5 −16.5 V

2.7 5.5 V

Power Supply Sensitivity

∆V

OUT

/∆ΑV

−65 dB

2.5 mA/channel Outputs unloaded

1.75 mA/channel AV

= 0 V, outputs unloaded

2.2 mA/channel Outputs unloaded

0.5 3 μA V

= DV

, V

= GND

Power Dissipation 310 mW ±16.5 V operation, outputs unloaded

115 mW 16.5 V operation, AV

= 0 V, outputs unloaded

Power-Down Currents

40 μA

300 nA

For specified performance, maximum headroom requirement is 0.9 V.

INL is measured from Code 512, Code 128, and Code 32 for the AD5754, the AD5734, and the AD5724, respectively.

Guaranteed by characterization; not production tested.

AD5724/AD5734/AD5754

Rev. 0 | Page 5 of 32

AC PERFORMANCE CHARACTERISTICS

= 4.5 V

to 16.5 V; AV

= −4.5 V

to −16.5 V, or 0 V; GND = 0 V; REFIN= 2.5 V; DV

= 2.7 V to 5.5 V; R

LOAD

= 2 kΩ;

LOAD

= 200 pF; all specifications T

MIN

to T

MAX

Table 2.

A, B Version

Parameter

Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 10 12 μs 20 V step to ±0.03% FSR

7.5 8.5 μs 10 V step to ±0.03% FSR

5 μs 512 LSB step settling (16-bit resolution)

Slew Rate 3.5 V/μs

Digital-to-Analog Glitch Energy 13 nV-sec

Glitch Impulse Peak Amplitude 35 mV

Digital Crosstalk 10 nV-sec

DAC-to-DAC Crosstalk 10 nV-sec

Digital Feedthrough 0.6 nV-sec

Output Noise

0.1 Hz to 10 Hz Bandwidth) 15 μV p-p 0x8000 DAC code

100 kHz Bandwidth 80 μV rms

Output Noise Spectral Density 320 nV/√Hz Measured at 10 kHz, 0x8000 DAC code

For specified performance, maximum headroom requirement is 0.9 V.

Guaranteed by design and characterization. Not production tested.

TIMING CHARACTERISTICS

= 4.5 V to 16.5 V; AV

= −4.5 V to −16.5 V, or 0 V; GND = 0 V; REFIN = 2.5 V; DV

= 2.7 V to 5.5 V; R

LOAD

= 2 kΩ; C

LOAD

= 200 pF;

all specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 3.

Parameter

1, 2, 3

Limit at t

MIN

, t

MAX

Unit Description

33 ns min SCLK cycle time

13 ns min SCLK high time

13 ns min SCLK low time

13 ns min

SYNC

falling edge to SCLK falling edge setup time

13 ns min

SCLK falling edge to SYNC

rising edge

100 ns min

Minimum SYNC

high time (write mode)

5 ns min Data setup time

0 ns min Data hold time

20 ns min

LDAC

falling edge to SYNC falling edge

20 ns min

SYNC

rising edge to LDAC falling edge

20 ns min

LDAC

pulse width low

10 μs typ DAC output settling time

20 ns min

CLR

pulse width low

2.5 μs max

CLR

pulse activation time

13 ns min

SYNC

rising edge to SCLK rising edge

40 ns max SCLK rising edge to SDO valid (C

L SDO

= 15 pF)

200 ns min

Minimum SYNC

high time (readback/daisy-chain mode)

Guaranteed by characterization; not production tested.

All input signals are specified with t

= t

= 5 ns (10% to 90% of DV

) and timed from a voltage level of 1.2 V.

See Figure 2, Figure 3, and Figure 4.

Daisy-chain and readback mode.

L SDO

= capacitive load on SDO output.

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