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Ballot Template Version draft rev. 8/11
© JEDEC 2011
COMMITTEE LETTER BALLOT
Committee: JC42.3
Committee Item Number: 1848.99A
Subject: DDR5 Full Spec Draft Rev0.5c
Background: All red and black items are for ballot, red text identifies the updates from the
previous ballot. Items in grey are not part of the ballot material and are for
reference only
Keywords: DDR5, Full Specification
DDR5 Proposal Item 1845.31A
Page 2 of 2
P R O P O S E D
REVISION HISTORY
Revision Author Date Status and Description
Rev0.1 C.Cox 12/5/17 Initial Format Rev0.1 - Includes all ballots through Q3’17
Rev0.3 C.Cox 2/28/18
Update to include all ballots through
Q1’18. TG consensus was to pro-actively add all the
current quarter ballots even though they haven’t officially been counted. Additionally, since
there were multiple errors with the 100+ page Mode Register Ballot, this draft contains the
proposed Fast Track update for Q2’18.
Rev0.5 C.Cox 6/30/18
Update to include all ballots thr
ough Q2’18. Includes all editorial comments from Q1’18 and
Q2’18 committee meetings. The Table of Contents page only highlights the new ballots,
editorial changes to many other sections were made, with identification of /Edits at the end
of the title ballot.
Main Ballot updates:
- Write Operation - Ballot#1845.22 w/Edits
- Command Truth Table - Ballot#1830.42E w/Edits
- x16 DRAM Package Ballout - Ballot#1845.77 w/Edits
- Connectivity Test Mode Update - Ballot#1845.06A w/Edits
- Asymmetric RON Control - Ballot#1845.59 w.Edits
- BL32 Ballot#1845.56 w/Destruction Edits, This ballot was split up into many parts to go to
Burst Order, Read Operation, Write Operation and Command Intervals. There
were also
many editorial
updates to other definitions to reflect these changes. All o
f the diagrams
wer
e updated to match the standard spec format.
- Reset and Init Sequence - Ballot#1845.20A w/Edits
- Frequency Change - Ballot#1848.36
- Mo
de Register Definition and content MR0 through MR255 w/Edits
- Read Operation - Ballot 1845.21 w/Edits
- Supply Rail Voltage Slew Rates - Ballot#1845.35 w/Edits
-tWTR_L Update - Ballot#1830.44A, This ballot updated Ch13, Timi
ng Parameters by
Speed Grade where the parameter for tWTR_L is held.
- Speed Bins (up to 4800) - Ballot#1830.35D w/Edits (Still needs down-binning)
- tDQSCK Update - Ballot#1830.75B
- CA Rx Voltage and Timings #1849.15A
- DC Operating Condition - Ballot#1848.24
- JM7 Verbal Forms and Terms added to define words such as SHALL and WILL.
NOTE: Temp Sensor Ballot#1845.76 -
Was NOT included - Committee agreed not to add
to Spec Dr
aft due to upcoming changes.
Rev0.5c C.Cox 7/9/18
Added missing tPPD Q3’17 Ballot#184
8.17, added to Timing Parameters by Speed Grade.
Ballot covered through 6400 though 5200+ tables not yet defined.
Added missing 3DS Q4’17 Ballot#1850.06 (Read and Write Command In
tervals) put into
3DS timing parameters by Speed Grade with reference markers in Read and Write Com-
mand Interval section,
Adding missing 3DS Q4’17 Ballot#1850.04 (3DS Refresh timings) blended into R
efresh
Definitions
Document Formating Legend
Colors used in this Document and what they mean:
RED - All Red text is defined as something that is NEW
BLACK - Is considered the standard or the current Ballot.
LIGHT GREY - All Light Grey text is defined as something that should be considered TBD. The content may be accurate or the same
as previous technologies but has not yet been reviewed or determined to be the working assumption.
Special NOTE: Some legacy diagrams that have not been updated may be BLACK or RED but that does not indicate that they are
new or current working assumption. In the case where there is a digram that is BLACK or RED, it is important to look at the section for
reference. If the section/heading is BLACK or RED, then it is as intended. If the section/heading is GREY, then assume its only an
artifact of the old diagram that could not easily be changed.
Proposed DDR5 Full spec (79-5) Item No. xxxx.yyy
Page 1
1. Scope ............................................................................................................................................................. 1
1.1 JM7 Verbal Forms and Terms ......................................................................................................................................... 2
2. DDR5 SDRAM Package, Pinout Description and Addressing........................................................................ 5
2.1 DDR5 SDRAM Row for X4, X8 - Q3’17 Ballot#1830.69B.......................................................................... 5
2.2 DDR5 SDRAM Ball Pitch - Q3’17 Ballot#1830.69B ................................................................................... 5
2.3 DDR5 SDRAM Columns for X4, X8 - Q3’17 Ballot#1830.69B................................................................... 5
2.4 DDR5 SDRAM X4/8 Ballout using MO-xxx - Q4’17 Ballot #1830.69C w/Edits .......................................... 6
2.5 DDR5 SDRAM X16 Ballout using MO-xxx - Q2’18 Ballot#1845.77 w/Edits .............................................. 7
2.6 Pinout Description - Q4’17 Ballot #1845.73 w/Edits .................................................................................. 8
2.7 DDR5 SDRAM Addressing - Q2’17 Item#1830.36B ................................................................................. 10
3. Functional Description .................................................................................................................................... 11
3.1 Simplified State Diagram - No Ballot.......................................................................................................... 11
3.2 Basic Functionality - No Ballot ................................................................................................................... 12
3.3 RESET and Initialization Procedure - Q2’18 Ballot 1845.20A w/Edits ....................................................... 13
3.3.1 Power-up Initialization Sequence ................................................................................................... 13
3.3.2 TBD - Reset Initialization with Stable Power .................................................................................. 15
3.3.3 Input Voltage Power-up and Power-Down Sequence - Q2’18 Ballot# 1848.35 w/Edits................. 16
3.4 Mode Register Definition - Q2’18 Ballot #1845.17C w/Edits......................................................................17
3.4.1 Mode Register Read (MRR)........................................................................................................... 17
3.4.2 Mode Register WRITE (MRW) ....................................................................................................... 20
3.4.3 Mode Register Truth Tables and Timing Constraints..................................................................... 20
3.5 Mode Registers - Q2’18 Ballot #1845.17C w/Edits.................................................................................... 23
3.5.1 Mode Register Assignment and Definition in DDR5 SDRAM........................................................ 23
3.5.2 MR0 (MA[7:0]=00H) - Q2’18 Ballot #1845.17C w/Edits ................................................................. 28
3.5.3 MR1 (MA [7:0] = 01H) - PDA Mode Details - Q3’17 Ballot #1845.35B........................................... 29
3.5.4 MR2 (MA [7:0] = 02H) - DQS Training w/Edits............................................................................... 30
3.5.5 MR3 (MA[7:0]=03H) - Functional Modes - Q3’17 Ballot #1845.33C w/Edits.................................. 31
3.5.6 MR4 (MA[7:0]=04H) - Refresh Settings - Q2’18 Ballot #1845.17C w/Edits.................................... 32
3.5.7 MR5 (MA[7:0]=05H) - IO Settings - Q2’18 Ballot #1830.36A w/Edits............................................. 33
3.5.8 MR6 (MA[7:0]=06H) - Write Recovery Time & tRTP - Q2’18 Ballot #1845.17C w/Edits ................ 34
3.5.9 MR7 (MA[7:0]=07H) - Blank - No Ballot ......................................................................................... 35
3.5.10 MR8 (MA[7:0]=08H) - Preamble / Postamble - Q2’18 Ballot #1845.17C w/Edits......................... 36
3.5.11 MR9 (MA[7:0]=09H) - VREF Configuration - Q2’18 Ballot #1845.17C w/Edits ............................ 37
3.5.12 MR10 (MA[7:0]=0AH) - VrefDQ Calibration Value - Q2’18 Ballot #1845.17C w/Edits ................. 38
3.5.13 MR11 (MA[7:0]=0BH) - Vref CA Calibration Value - Q2’18 Ballot #1845.17C w/Edits................. 39
3.5.14 MR12 (MA [7:0] = 0CH) - tCCD_L - Q2’18 Ballot #1845.17C w/Edits.......................................... 40
3.5.15 MR14 (MA[7:0]=0EH) - Transparency ECC Configuration........................................................... 41
3.5.16 MR15 (MA[7:0]=0FH) - ECS Error Threshold............................................................................... 41
3.5.17 MR16 (MA [7:0] = 10H) - Address of Row with Max Errors 1....................................................... 42
3.5.18 MR17 (MA [7:0] = 11H) - Address of Row with Max Errors 2....................................................... 42
3.5.19 MR18 (MA [7:0] = 12H) - Address of Row with Max Errors 3....................................................... 42
3.5.20 MR19 (MA [7:0] = 13H) - Code Word Errors ................................................................................43
3.5.21 MR20 (MA [7:0] = 14H) - Error Count of Rows 1.......................................................................... 43
3.5.22 MR21 (MA [7:0] = 15H) - Error Count of Rows 2.......................................................................... 43
3.5.23 MR22 (MA [7:0] = 16H) - Error Count of Rows 3.......................................................................... 44
3.5.24 MR23 (MA [7:0] = 17H) - PPR Settings - Q1’17 Ballot #1845.41 w/Edits .................................... 45
3.5.25 MR24 (MA [7:0] = 18H) - PPR Guard Key - Q2’18 Ballot #1845.17B Proposal ........................... 45
3.5.26 MR25 (MA[7:0]=19H) - Read Training Mode Settings - Q2’18 Ballot #1845.17C w/Edits............ 46
3.5.27 MR26 (MA[7:0]=1AH) - Read Pattern Data0 / LFSR0 - Q1’17 Ballot #1845.42 ........................... 47
3.5.28 MR27 (MA[7:0]=1BH) - Read Pattern Data1 / LFSR1 - Q1’17
Ballot #1845.42........................... 47
3.5.29 MR28 (MA[7:0]=1CH) - Read Pattern Invert DQL7:0 (DQ7:0) - Q1’17 Ballot #1845.42 .............. 48
3.5.30 MR29 (MA[7:0]= DH) - Read Pattern Invert DQU7:0 (DQ15:8) - Q1’17 Ballot #1845.42............. 48
3.5.31 MR30 (MA[7:0]=1EH) - Read LFSR Assignments - Q1’17 Ballot #1845.42................................. 49
3.5.32 MR31 (MA[7:0]=1FH) - Read Training Pattern Address - Q1’17 Ballot #1845.42........................ 49
3.5.33 MR32 (MA[7:0]=20H) - CK ODT - Q2’18 Ballot #1845.17C w/Edits............................................. 50
3.5.34 MR33 (MA[7:0]=21H) - CA, CS ODT - Q2’18 Ballot #1845.17C w/Edits...................................... 51
3.5.35 MR34 (MA[7:0]=22H) - RTT_PARK & RTT_WR - Q2’18 Ballot #1845.17C w/Edits .................... 52
3.5.36 MR35 (MA[7:0]=23H) - RTT_NOM_WR & RTT_NOM_RD - Q2’18 Ballot #1845.17C w/Edits.... 53
3.5.37 MR36 (MA[7:0]=24H) - RTT Loopback - Q2’18 Ballot #1845.17C w/Edits................................... 54
3.5.38 MR37 (MA[7:0]= 25H) - ODTL Write Control Offset - Q2’18 Ballot #1845.17C w/Edits............... 55
3.5.39 MR38 (MA[7:0]=26H) - ODTL NT Write Control Offset - Q2’18 Ballot #1845.17C w/Edits .......... 56
3.5.40 MR39 (MA[7:0]=27H) - ODTL NT Read Control Offset - Q2’18 Ballot #1845.17C w/Edits.......... 57
