clr:IN STD_LOGIC;
cat:OUT STD_LOGIC_VECTOR( 5 DOWNTO 0 );
seg:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END seg7;
ARCHITECTURE bodyofseg7 OF seg7 IS
SIGNAL tem:INTEGER RANGE 0 TO 1;
SIGNAL num:INTEGER RANGE 0 TO 9;
SIGNAL cat0:STD_LOGIC_VECTOR( 5 DOWNTO 0 );
BEGIN
PROCESS(clk1000)
BEGIN
IF (clk1000'EVENT AND clk1000 = '1') THEN
IF start='1' THEN
CASE tem IS
WHEN 0
cat0<="111101";num<=INTEGER((time_cnt)MOD(10));tem<=tem+1;
WHEN 1
cat0<="111110";num<=INTEGER(time_cnt/10);tem<=0;
WHEN OTHERS => cat0<="111111";tem<=0;
END CASE;
cat<=cat0;
=>
=>
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