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I
Design of MASH 2-2 Sigma-Delta modulators
and its Simulation in MATLAB
Abstract
A major challenge for mixed signal circuit design is to balance between system
simulation time and accuracy for the real non-ideal effects. Sigma-Delta modulator is such a
kind of circuit that is very popular in signal processing and communication systems nowadays.
Its behavioral model is constructed and analyzed of non-idealities are included in this thesis.
Almost all the non-idealities are applied into the proposed wide band architecture, which is not
mentioned before. The behavioral model of a fourth order 2-2 MASH sigma delta modulator
for WLAN is presented. The model is built by using MATLAB/SIMULINK environment. It
considers most of the sigma delta modulator non-idealities, such as thermal noise of switches,
clock jitter, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth,
slew rate and saturation voltages). Simulation results show the validity of the proposed models.
These models introduce balance between good accuracy and fast simulation speed which
improves the system performance and efficiency.
Keywords: Sigma-Delta modulator, MATLAB/SIMULINK, MASH, clock jitter, slew
rate.
II
Mash 2-2 Sigma-Delta
调制器的设计及其
MATLAB
仿真
摘 要
如何在电路系统仿真的时间和精度之间取得平衡以达到真正的非理想效果是混合
信号电路设计的一个主要挑战。Sigma-Delta 调制器是目前在信号处理和通信系统中非
常流行的一种电路。本文提出了一种适用于无线局域网的四阶2-2 MASH-sigma-delta调
制器的行为模型,并对其非理想因素进行了分析,并在 MATLAB/SIMULINK环境下建
立了该模型。模型考虑了大多数sigma-delta调制器的非理想特性,如开关的热噪声、时
钟抖动和运算放大器参数(白噪声、有限直流增益、有限带宽、转换速率和饱和电
压)。仿真结果表明了本文所提的模型的有效性,模型兼顾了高精度和高仿真速度,
提高了系统的性能和效率。
关键词:Sigma-Delta 调制器,MATLAB/SIMULINK, MASH, 时钟抖动, 转换速率
Contents
Chapter 1 Introduction…...………………………………………………………………………..1
1.1 ADC Fundamentals……………………………………………………………….………..1
1.2 ADC architectures..…..…………………………………………………………………….4
1.3 Literature Review…..……..……………………………………………………….……….5
1.4 Classification of ΔΣ Modulators…....…………………………………………….………..8
1.5 Objectives…..…………...………………………………………………………………….9
1.6 Design methodologies……...……………………………………………………….…….10
1.7 Overview……..………….………………………………………………………….…….11
Chapter 2 Cascade Multi-Stage Noise-Shaping (MASH) Modulators………….……………….12
2.1 Introduction….……………………………………………………………………………12
2.2 Quantization Noise Reduction by Oversampling…..………..……………………...…….12
2.3 Noise-Shaping…....…………………………………………………………………..……15
2.4 Second-Order and High-Order Delta Sigma Modulators…….……………………...…….22
2.5 (MASH) Modulator……………………………………………………….......…………...25
Chapter 3 Design and Simulation………………………………………………………………..28
3.1 Introduction………………………………………………………………………………..28
3.2 Σ-Δ Modulator Design for WLAN Application………………………………………..….28
3.3 Non-Idealities Models Design of Σ-Δ Modulator.…………………………………….…..30
3.3.1 CLOCK JITTER………………………………………………………………...…….31
3.3.2 Integrator Noise.……..……………………………………………………………..…32
3.3.2.1 Switches Thermal Noise……………………..…………..……………...………34
3.3.2.2 Op-Amp Noise….…………………………………………………………...….35
3.3.3 Integrator Non-Idealities…….……………………...…………………………..……..35
3.3.3.1 Dc Gain………..………………………………………………………….……..36
3.3.3.2 Bandwidth and Slew Rate….…………………………………………..………..36
3.3.3.3 Saturation…………….………….………………………………………………39
3.4 Simulation Results…………..…..……………………………………………………...….39
3.4.1 Ideal Modulator Model……………….………………………………………………..41
3.4.2 Clock Jitter Effect………………………………………………………………..……..42
3.4.3 Switches Thermal Noise Effect……………………………………..………………….43
3.4.4 Op-Amp Noise Effect……………..……………………………………………………44
3.4.5 Integrator Non-Idealities Effect…..…………………………………………………….45
3.4.5.1 DC Gain Effect………...…………………………………………………………45
3.4.5.2 Bandwidth and Slew Rate Effect…………………………...…………………….46
3.4.5.3 Saturation Effect……………………………………………………...…………..48
3.4.6 Total Noise Effect (All non-idealities included) …………………….……..………….49
3.5 Discussion……………………………………………………………………….…………51
Chapter 4 Conclusions and Future Works……………………………………………………….52
4.1 Conclusion…………………………………………………………………………………52
4.2 Future works……………………………………………………………………………….52
References………………………………………………………………………………………..53
Acknowledgment……………………………………...…………………………………………55
Appendix A………………………………………………………………………………………56
List of figures
Figure1.1: ADC basic block diagram and Analog-to-Digital conversion process………………...3
Figure 1.2: (A) 6-level quantizer characteristic and its quantization error, (B) equivalence of the
quantizer block diagram with its simplified linear model accounting for the injection of a uniformly
distributed white noise……………………………………………………………......……………3
Figure 1.3: Murmann survey of ADC performance: representation on the ENOB versus signal
bandwidth plane………………………...…………………………………………………………6
Figure 1.4: Murmann survey of ADC performance: representation on the energy-per-conversion
versus the ENOB…………………………………………………………………………………..8
Figure 2.1: Estimating the quantizer input from its output sequence…………………………….13
Figure 2.2: (a) Improved y by digitally filtering of v, (b) Comparison of y and y
^
………………..13
Figure 2.3: Signal chain that employs oversampling to reduce quantization noise, and spectra of v,
y
^
, and v
1
………………………………………………………………………………………….14
Figure 2.4: A simple negative-feedback amplifier…………………………………………….....15
Figure 2.5: Associating e with quantization error………………………………………….…….15
Figure 2.6: A physically realizable discrete-time feedback loop should have at least one sample
delay. e is the quantization error……………………………………………………………….…16
Figure 2.7: Pole locations of the system of Figure 2.6 for small and large A…………………......17
Figure 2.8: A negative feedback system where the output quantization noise is attenuated at low
frequencies…………………………………………………………………………………….…17
Figure 2.9: Magnitude of the NTF of a first-order noise-shaping quantizer on the (a) linear and (b)
log scales…………..……………………………………………………………………….…….18
Figure 2.10: (a) Signal chain with a first-order ΔΣ loop. (b) Pole-zero map of the system and the
impulse response corresponding to the NTF……………………………………………………...19
Figure 2.11: (a) u and v (b) u and v after being filtered with a digital low pass filter. (c) Error
between the input and filtered output……………………………………………………………..21
Figure 2.12: (a) Synthesis of a second-order ΔΣ modulator and (b) equivalent representation…..23
Figure 2.13: Second-Order ΔΣ modulator with feedback delays pushed into the integrators…….23
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