library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity notetabs is
port(clk:in std_logic;
toneindex:out std_logic_vector(3 downto 0));
end;
architecture one of notetabs is
component rom
port(address:in std_logic_vector(7 downto 0);
clock:in std_logic;
q:out std_logic_vector(3 downto 0));
end component;
signal msjy:std_logic_vector(1 downto 0);
signal counter:std_logic_vector(7 downto 0);
begin
process(clk)
begin
if counter=138 then counter<="00000000";
elsif (clk'event and clk='1') then counter<=counter+1;
end if;
end process;
process(clk)
begin
if msjy="11" then msjy<="00";f<='1';
elsif clk'event and clk='1' then msjy<=msjy+1;
end if;
end process;
u1:rom port map(address=>counter,q=>toneindex,clock=>clk);
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