Copyright © 2006, 2009, 2012, 2013 ARM Limited or its affiliates. All rights reserved.
ARM IHI 0031C (ID080813)
ARM
®
Debug Interface
Architecture Specification
ADIv5.0 to ADIv5.2
ii Copyright © 2006, 2009, 2012, 2013 ARM Limited or its affiliates. All rights reserved. ARM IHI 0031C
Non-Confidential ID080813
ARM Debug Interface Architecture Specification
ADIv5.0 to ADIv5.2
Copyright © 2006, 2009, 2012, 2013 ARM Limited or its affiliates. All rights reserved.
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The following changes have been made to this book.
This book includes information originally published in the ARM
®
Debug Interface v5 Architecture Specification ADIv5.1
Supplement (DSA09-PRDC-008772).
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Change History
Date Issue Confidentiality Change
8 February 2006 A Non-Confidential First issue, for ADIv5.
14 May 2012 B Confidential Beta Second issue, for ADIv5.0 to ADIv5.2.
08 August 2013 C Non-Confidential Final Third issue, for ADIv5.0 to ADIv5.2.
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Contents
ARM Debug Interface Architecture Specification
ADIv5.0 to ADIv5.2
Preface
About this book ............................................................................................................ x
Using this book ........................................................................................................... xi
Conventions ............................................................................................................... xii
Additional reading ..................................................................................................... xiv
Feedback ................................................................................................................... xv
Chapter 1 Introduction
1.1 About the ARM Debug Interface version 5 (ADIv5) ............................................... 1-18
1.2 The function of the ARM Debug Interface .............................................................. 1-20
1.3 The subdivisions of an ARM Debug Interface v5 implementation ......................... 1-22
1.4 The external interface, the Debug Port (DP) .......................................................... 1-23
1.5 The resource interface, the Access Ports (APs) .................................................... 1-24
1.6 Design choices and implementation examples ...................................................... 1-28
Chapter 2 The Debug Port (DP)
2.1 Common Debug Port features ............................................................................... 2-34
2.2 DP architecture versions ........................................................................................ 2-40
2.3 DP register descriptions ......................................................................................... 2-45
2.4 System and debug power and debug reset control ............................................... 2-62
Chapter 3 The JTAG Debug Port (JTAG-DP)
3.1 The Debug TAP State Machine introduction .......................................................... 3-70
3.2 The scan chain interface ........................................................................................ 3-71
3.3 IR scan chain and IR instructions .......................................................................... 3-74
3.4 DR scan chain and DR registers ............................................................................ 3-78
