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ARM官方有关调试协议(SWD, JTAG)的指导手册
Confidentiality Stat This document is Non-Confidential. Any use by you is subject to the terms of the agreement between you and arm or the terms of the agreement between you and the party authorised by arm to disclose this document to you Product stat The information in this document is final, that is for a developed product Web addr ARM IHI O031C Copyright o 2006, 2009, 2012, 2013 ARM Limited or its affiliates. All rights reserved III D080813 Non-Confidential Copyright o 2006, 2009, 2012, 2013 ARM Limited or its affiliates. All rights reserved ARM IHI 0031C Non-Confidential Contents ARM Debug Interface Architecture Specification ADIv5.0 to ADIv52 Preface About this book Using this book Conventions Additional read Feedback Chapter 1 Introduction 1 About the ARM Debug Interface version 5(ADlv5) 1-18 The function of the ARM Debug Interface 1.3 The subdivisions of an aRM Debug Interface v5 implementation 1.4 The external intertace, the Debug Port(DP) 1-23 The resource interface, the Access Ports(APs) Design choices and implementation examples 1-28 Chapter 2 The Debug Port (DP 2.1 Common Debug Port features 2-34 2.2 DP architecture versions 2-40 DP register descriptions 2-45 2. 4 System and debug power and debug reset control ... Chapter 3 The JTAG Debug Port JTAG-DP The Debug taP State Machine introduction 3-70 The scan chain interface 3-71 R scan chain and ir instructions 3-74 3. 4 DR scan chain and dR registers .. ARM IHI 0031C Copyright 2006, 2009, 2012, 2013 AR/ Limited or its affiliates. All rights reserved D080813 Non-Confidential Chapter 4 The Serial Wire Debug Port (SW-DP 4.1 Introduction to the Serial Wire Debug Port 4-88 4.2 Introduction to the ARM Serial Wire Debug(SWD)protocol 4-89 4.3 Serial Wire Debug protocol operation 4-93 4.4 Serial Wire Debug interface 4-104 Chapter 5 The Serial Wire/JTAG Debug Port (SWJ-DP) 5.1 Serial Wire/JTAG Debug Port (SWJ-DP) 5.2 SWD and jTAG select mechanism 5-110 53 Dormant operation 5-113 5.4 Restriction on switching 5-120 Chapter 6 The Access Port (AP) 6.1 Overview of Access Ports(APs) 6-122 6.2 Selecting and accessing an AP 6.3 The Programmers' Model for Access Port (AP)registers 6-124 Chapter 7 The Memory Access Port MEM-AP) 7 About the function of a Memory Access Port (MEM-AP) 7-128 7.2 MEM-AP functions .7-132 Implementing a MEM-AP 7-142 7.4 MEM-AP examples of pushed-verify and pushed-compare .7-144 7.5 MEM-AP register summary 7-146 7.6 MEM-AP register descriptions ..7-147 Chapter 8 The JTAG Access Port ( JTAG-AP 8.1 Overview of the JTAG Access Port (JTAG-AP) 8-162 8.2 Operation of the jTAG-AP 8-166 8.3 The JTAG Engine Byte Command Protocol 8-169 8.4 JTAG-AP register summary 8-176 8.5 JTAG-AP register descriptions .8-177 Chapter 9 Component and Peripheral ID Registers 9. Component and Peripheral ID registers 9-186 9. 2 The Component ID Registers 9-187 9.3 The Peripheral ID Registers 9-191 Chapter 10 ROM Tables 10.1 ROM Table overview 10.2 ROM Table entries 10-202 10. 3 The MEMTYPE register 0-205 10.4 Component and peripheral id Registers 10-206 10.5 ROM Table hierarchies 10-207 Appendix A Standard Memory Access Port Definitions A.1 ntroduction A-212 A2 AMBA AX 3 and ax4 A-213 A.3 AMBA AX 4 With ACE-Lite A215 A.4 AMBA AHB A217 A. 5 AMBA APB2 and aPb3 A-218 Appendix B Cross-over with the arm architecture B.1 Introduction B-220 B.2 ARMv6-M architecture B3 ARMV7-M architecture profile B-222 B4 ARMV7-A without Large Physical Address Extension and ARMv7-R architecture profiles Copyright o 2006, 2009, 2012, 2013 ARM Limited or its affiliates. All rights reserved ARM IHI 0031C Non-Confide D080813 Contents B5 ARMv7-A with Large Physical Address Extension and ARMv8-A architecture profiles B6 Summary of the required ADlv5 implementations B-225 Appendix C Pseudocode definition C.1 About ARM pseudocode C228 Data types C-229 Expressions C-233 C.4 Operators and built-in functions C.5 Statements and program structure…… C-240 Glossary ARM IHI 0031C Copyright 2006, 2009, 2012, 2013 AR/ Limited or its affiliates. All rights reserved D080813 Non -Confidentia/ Contents Copyright o 2006, 2009, 2012, 2013 ARM Limited or its affiliates. All rights reserved ARM IHI 0031C Non-Confiden D080813 Preface This preface introduces the ARM Debug Interface Architecture specification, A/v 5.0 to AD/v5.2. It contains the following sections About this book on page x Using this book on pagc xi Conventions on page Xi Additional reading on page xiv. Feedback on page xv ARM IHI 0031C Copyright o 2006, 2009, 2012, 2013 ARM Limited or its affiliates. All rights reserved D080813 Non-Confidential About this book About this book This is thc Architecture Specification for thc ARM Debug Interface v5, ADlv5 0 to ADIv5 2(ADIv5 Intended audience This specification is written for system designers and engineers who are specifying, designing or implementing a debug interface to the ADIvs architecture specification. This includes system designers and engineers who are specifying, designing or implementing a Syslem-Un-Chip(Soc)that incorporates a debug interface that complies with the adIv5 specification This specification is also intended for engineers who are working with a debug interface that conforms to the aDlv specification. This includes designers and engineers who are Specifying, designing or implementing hardware debuggers Specifying, designing or writing debug software These engineers have no control over the design decisions made in the aDlv5 interface implementation to which they are connecting but must be able to identify the adls interface components present, and understand how they This specification provides an architectural description of an ADIv5 interface. It does not describe how to implement the interface Copyright o 2006, 2009, 2012, 2013 ARM Limited or its affiliates. All rights reserved ARM IHI 0031C Non-Confidential

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