1.VHDL³ÌÐò
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity corna is
port(
clr,af,aj,bf,bj,clk:in std_logic;
shift:out std_logic_vector(15 downto 0);
ah,al,bh,bl:out std_logic_vector(3 downto 0)
q:out std_logic_vector(6 downto 0);
sellread:out std_logic_vector(3 downto 0);
);
end corna;
architecture corna_arc of corna is
signal amark,bmark:integer;
signal clk1:std_logic;
signal fen:std_logic_vector(9 downto 0);
begin
process
begin
wait until clk='1';
fen<=fen+1;
clk1<=fen(7);
end process;
process(clr,clk1)
variable a,b:std_logic;
variable she:std_logic_vector(15 downto 0);
begin
if clr='0' then
a:='0';
b:='0';
she:="0000000000000000";
amark<=0;
bmark<=0;
elsif clk1'event and clk1='1'then
if a='0'and b='0'and af='1'then
a:='1';
she:="1000000000000000";
elsif a='0' and b='0' and bf='1' then
b:='1';
she:="0000000000000001";
elsif a='1' and b='0' then
if she>128 then
if bj='1' then
amark<=amark+1;
a:='0';
b:='0';
she:="0000000000000000";
else
she:='0'&she(15 downto 1);
end if;
elsif she=0 then
amark<=amark+1;
a:='0';
b:='0';
else
if bj='1'then
