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通用串口是远程通信接口,在数字系统中使用很普遍,是一个很重要的部件本设计使用了Verilog HDL语言描述硬件功能,利用Quartus II 13.0在FPGA 芯片上综合描述,利用模块化设计方法设计 UART(通用异步收发器)的各个模块。其中包括波特率控制、SRAM存储、UART数据接收器、UART数据发送器、数码管显示,本设计采用外部时钟50MHZ,波特率4800和9600可设定。资源中附有代码和quartusII的工程文件,由于作者水平有限,若有不足之处欢迎指正。
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基于FPGA的uart接口电路设计verilog实现 (125个子文件)
uart_top.vpr.ammdb 570B
uart_top.root_partition.cmp.ammdb 552B
uart_top.map.ammdb 123B
uart_top.ace_cmp.bpm 684B
uart_top.cmp.bpm 672B
uart_top.map.bpm 642B
uart_top.cmp.cdb 29KB
uart_top.ace_cmp.cdb 28KB
uart_top.rtlv_sg.cdb 19KB
uart_top.root_partition.cmp.cdb 14KB
uart_top.sgdiff.cdb 11KB
uart_top.root_partition.map.cdb 10KB
uart_top.map.cdb 10KB
uart_top.(6).cnf.cdb 7KB
uart_top.(4).cnf.cdb 6KB
uart_top.(3).cnf.cdb 5KB
uart_top.(1).cnf.cdb 3KB
uart_top.(7).cnf.cdb 2KB
uart_top.map_bb.cdb 2KB
uart_top.(0).cnf.cdb 1KB
uart_top.root_partition.map.reg_db.cdb 1KB
uart_top.(5).cnf.cdb 1KB
uart_top.(2).cnf.cdb 1KB
uart_top.root_partition.map.hbdb.cdb 1KB
uart_top.rtlv_sg_swap.cdb 1KB
uart_top.eco.cdb 164B
logic_util_heursitic.dat 9KB
uart_top.db_info 140B
uart_top.db_info 140B
uart_top.tiscmp.slow_1200mv_0c.ddb 170KB
uart_top.tiscmp.slow_1200mv_85c.ddb 169KB
uart_top.tiscmp.fast_1200mv_0c.ddb 168KB
uart_top.tiscmp.fastest_slow_1200mv_0c.ddb 123KB
uart_top.tiscmp.fastest_slow_1200mv_85c.ddb 123KB
uart_top.asm_labs.ddb 8KB
uart_top.tis_db_list.ddb 235B
uart_top.pti_db_list.ddb 177B
uart_top.root_partition.cmp.dfp 33B
uart_top.done 26B
uart_top.root_partition.map.dpi 1KB
uart_top.root_partition.map.hbdb.hb_info 46B
uart_top.pre_map.hdb 15KB
uart_top.rtlv.hdb 15KB
uart_top.cmp.hdb 15KB
uart_top.sgdiff.hdb 15KB
uart_top.ace_cmp.hdb 14KB
uart_top.root_partition.cmp.hdb 14KB
uart_top.root_partition.map.hdb 14KB
uart_top.map.hdb 14KB
uart_top.root_partition.map.hbdb.hdb 14KB
uart_top.map_bb.hdb 10KB
uart_top.(4).cnf.hdb 3KB
uart_top.(7).cnf.hdb 2KB
uart_top.(6).cnf.hdb 1KB
uart_top.(1).cnf.hdb 1KB
uart_top.(3).cnf.hdb 1KB
uart_top.(0).cnf.hdb 962B
uart_top.(5).cnf.hdb 874B
uart_top.(2).cnf.hdb 848B
uart_top.hier_info 11KB
uart_top.hif 768B
uart_top.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd 729KB
uart_top.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd 728KB
uart_top.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd 723KB
uart_top.lpc.html 2KB
uart_top.cmp.idb 16KB
uart_top.ipinfo 163B
uart_top.jdi 226B
uart_top.root_partition.map.kpt 3KB
uart_top.map.kpt 3KB
uart_top.cmp_merge.kpt 209B
uart_top.root_partition.cmp.kpt 205B
uart_top.cmp.kpt 203B
uart_top.cmp.logdb 12KB
uart_top.map.logdb 4B
uart_top.root_partition.cmp.logdb 4B
uart_top.map_bb.logdb 4B
FPGA_yang.pdf 1.41MB
uart_top.pin 32KB
prev_cmp_uart_top.qmsg 95KB
uart_top.map.qmsg 32KB
uart_top.sta.qmsg 24KB
uart_top.fit.qmsg 19KB
uart_top.asm.qmsg 2KB
uart_top.qpf 1KB
uart_top.qsf 4KB
uart_top.qws 613B
uart_top.root_partition.cmp.rcfdb 13KB
uart_top.sta.rdb 40KB
uart_top.cmp.rdb 23KB
uart_top.routing.rdb 5KB
uart_top.asm.rdb 1KB
uart_top.map.rdb 1KB
uart_top.lpc.rdb 572B
uart_top.pplq.rdb 232B
README 653B
uart_top.sta.rpt 505KB
uart_top.fit.rpt 158KB
uart_top.map.rpt 47KB
uart_top.flow.rpt 8KB
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