EnhancedHostControllerInterfaceSpecificationforUniversalSerialBus资源-CSDN文库

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Enhanced Host Controller Interface Specification for Universal Serial Bus 1. INTRODUCTION...............................................................................................1 1.1 EHCI Product Compliance.................................................................................................................2 1.2 Architectural Overview.......................................................................................................................2 1.2.1 Interface Architecture....................................................................................................................4 1.2.2 EHCI Schedule Data Structures.....................................................................................................5 1.2.3 Root Hub Emulation......................................................................................................................5 2. REGISTER INTERFACE ..................................................................................7 2.1 PCI Configuration Registers (USB)...................................................................................................8 2.1.1 PWRMGT ? PCI Power Management Interface..........................................................................8 2.1.2 CLASSC ? CLASS CODE REGISTER......................................................................................9 2.1.3 USBBASE ? Register Space Base Address Register..................................................................9 2.1.4 SBRN ? Serial Bus Release Number Register.............................................................................9 2.1.5 Frame Length Adjustment Register (FLADJ)..............................................................................10 2.1.6 Port Wake Capability Register (PORTWAKECAP)...................................................................11 2.1.7 USBLEGSUP ? USB Legacy Support Extended Capability.....................................................11 2.1.8 USBLEGCTLSTS ? USB Legacy Support Control/Status........................................................12 2.2 Host Controller Capability Registers...............................................................................................13 2.2.1 CAPLENGTH ? Capability Registers Length...........................................................................13 2.2.2 HCIVERSION ? Host Controller Interface Version Number....................................................14 2.2.3 HCSPARAMS ? Structural Parameters.....................................................................................14 2.2.4 HCCPARAMS ? Capability Parameters....................................................................................15 2.2.5 HCSP-PORTROUTE ? Companion Port Route Description.....................................................16 2.3 Host Controller Operational Registers............................................................................................17 2.3.1 USBCMD ? USB Command Register.......................................................................................18 2.3.2 USBSTS ? USB Status Register................................................................................................21 2.3.3 USBINTR ? USB Interrupt Enable Register..............................................................................22 2.3.4 FRINDEX ? Frame Index Register............................................................................................23 2.3.5 CTRLDSSEGMENT ? Control Data Structure Segment Register............................................24 2.3.6 PERIODICLISTBASE ? Periodic Frame List Base Address Register......................................24 2.3.7 ASYNCLISTADDR ? Current Asynchronous List Address Register.......................................25 2.3.8 CONFIGFLAG ? Configure Flag Register................................................................................25 2.3.9 PORTSC ? Port Status and Control Register.............................................................................26 3. DATA STRUCTURES.....................................................................................31 3.1 Periodic Frame List...........................................................................................................................31 3.2 Asynchronous List Queue Head Pointer..........................................................................................32 3.3 Isochronous (High-Speed) Transfer Descriptor (iTD)....................................................................33 USB 2.0 i EHCI Revision 1.0 3/12/2002 3.3.1 Next Link Pointer.........................................................................................................................33 3.3.2 iTD Transaction Status and Control List......................................................................................34 3.3.3 iTD Buffer Page Pointer List (Plus).............................................................................................35 3.4 Split Transaction Isochronous Transfer Descriptor (siTD)...........................................................36 3.4.1 Next Link Pointer.........................................................................................................................37 3.4.2 siTD Endpoint Capabilities/Characteristics.................................................................................37 3.4.3 siTD Transfer State......................................................................................................................38 3.4.4 siTD Buffer Pointer List (plus)....................................................................................................39 3.4.5 siTD Back Link Pointer...............................................................................................................40 3.5 Queue Element Transfer Descriptor (qTD).....................................................................................40 3.5.1 Next qTD Pointer.........................................................................................................................41 3.5.2 Alternate Next qTD Pointer.........................................................................................................41 3.5.3 qTD Token...................................................................................................................................42 3.5.4 qTD Buffer Page Pointer List......................................................................................................45 3.6 Queue Head........................................................................................................................................46 3.6.1 Queue Head Horizontal Link Pointer...........................................................................................46 3.6.2 Endpoint Capabilities/Characteristics..........................................................................................47 3.6.3 Transfer Overlay..........................................................................................................................49 3.7 Periodic Frame Span Traversal Node (FSTN)................................................................................51 3.7.1 FSTN Normal Path Pointer..........................................................................................................51 3.7.2 FSTN Back Path Link Pointer......................................................................................................52 4. OPERATIONAL MODEL................................................................................53 4.1 Host Controller Initialization............................................................................................................53 4.2 Port Routing and Control..................................................................................................................54 4.2.1 Port Routing Control via EHCI Configured (CF) Bit..................................................................55 4.2.2 Port Routing Control via PortOwner and Disconnect Event.......................................................56 4.2.3 Example Port Routing State Machine..........................................................................................57 4.2.4 Port Power....................................................................................................................................57 4.2.5 Port Reporting Over-Current........................................................................................................58 4.3 Suspend/Resume................................................................................................................................59 4.3.1 Port Suspend/Resume..................................................................................................................59 4.4 Schedule Traversal Rules..................................................................................................................61 4.4.1 Example - Preserving Micro-Frame Integrity..............................................................................62 4.5 Periodic Schedule Frame Boundaries vs Bus Frame Boundaries..................................................64 4.6 Periodic Schedule...............................................................................................................................66 4.7 Managing Isochronous Transfers Using iTDs.................................................................................67 4.7.1 Host Controller Operational Model for iTDs...............................................................................67 4.7.2 Software Operational Model for iTDs.........................................................................................69 4.8 Asynchronous Schedule.....................................................................................................................71 4.8.1 Adding Queue Heads to Asynchronous Schedule........................................................................71 4.8.2 Removing Queue Heads from Asynchronous Schedule..............................................................72 4.8.3 Empty Asynchronous Schedule Detection...................................................................................74 ii USB 2.0 EHCI Revision 1.0 3/12/2002 4.8.4 Restarting Asynchronous Schedule Before EOF.........................................................................74 4.8.5 Asynchronous Schedule Traversal : Start Event..........................................................................76 4.8.6 Reclamation Status Bit (USBSTS Register)................................................................................77 4.9 Operational Model for Nak Counter................................................................................................77 4.9.1 Nak Count Reload Control...........................................................................................................78 4.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads....................................................79 4.10.1 Fetch Queue Head........................................................................................................................80 4.10.2 Advance Queue............................................................................................................................81 4.10.3 Execute Transaction.....................................................................................................................81 4.10.4 Write Back qTD...........................................................................................................................86 4.10.5 Follow Queue Head Horizontal Pointer.......................................................................................86 4.10.6 Buffer Pointer List Use for Data Streaming with qTDs...............................................................86 4.10.7 Adding Interrupt Queue Heads to the Periodic Schedule.............................................................88 4.10.8 Managing Transfer Complete Interrupts from Queue Heads.......................................................88 4.11 Ping Control.......................................................................................................................................88 4.12 Split Transactions..............................................................................................................................89 4.12.1 Split Transactions for Asynchronous Transfers...........................................................................90 4.12.2 Split Transaction Interrupt...........................................................................................................92 4.12.3 Split Transaction Isochronous....................................................................................................103 4.13 Host Controller Pause......................................................................................................................114 4.14 Port Test Modes...............................................................................................................................114 4.15 Interrupts..........................................................................................................................................115 4.15.1 Transfer/Transaction Based Interrupts.......................................................................................115 4.15.2 Host Controller Event Interrupts................................................................................................117 5. EHCI EXTENDED CAPABILITIES...............................................................121 5.1 EHCI Extended Capability: Pre-OS to OS Handoff Synchronization........................................121 APPENDIX A. EHCI PCI POWER MANAGEMENT INTERFACE......................125 A.1 PCI Power Management Register Interface..................................................................................125 A.1.1 Power State Transitions.............................................................................................................126 A.1.2 Power State Definitions.............................................................................................................126 A.1.3 PCI PME# Signal.......................................................................................................................127 APPENDIX B. EHCI 64-BIT DATA STRUCTURES............................................129 APPENDIX C. DEBUG PORT.............................................................................133 C.1 Locating the Debug Port..................................................................................................................133 C.2 Using the Debug Port Fields............................................................................................................134 C.3 USB2 Debug Port Register Interface..............................................................................................134 USB 2.0 iii EHCI Revision 1.0 3/12/2002 C.3.1 Debug Port Control Register......................................................................................................135 C.3.2 USB PIDs Register.....................................................................................................................137 C.3.3 Data Buffer.................................................................................................................................137 C.3.4 Device Address Register............................................................................................................138 C.4 Operational Model...........................................................................................................................138 C.4.1 OUT/SETUP Transactions.........................................................................................................139 C.4.2 IN transactions...........................................................................................................................139 C.4.3 Debug Software Startup.............................................................................................................139 C.4.4 Finding the Debug Peripheral....................................................................................................140 APPENDIX D. HIGH BANDWIDTH ISOCHRONOUS RULES............................141

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Enhanced Host Controller Interface Specification for

Universal Serial Bus

Date:

March 12, 2002

Revision:

1.0

EHCI Revision 1.0 3/12/2002

USB 2.0

THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY

WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR

PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR

SAMPLE. Information in this specification is provided in connection with Intel products. No license, express

or implied, by estoppel or otherwise, to any intellectual property rights is granted herein, except that a license

is hereby granted to copy and reproduce this specification for internal use only.

Contact Intel for information on further licensing agreements and requirements.

Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of

information in this specification. Except as provided in Intel’s Terms and Conditions of Sale for such

products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating

to sale and/or use of Intel products including liability or warranties relating to fitness for a particular

purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel

products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to documents, specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved"

or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for

conflicts or incompatibilities arising from future changes to them.

Contact your local Intel sales office or your distributor to obtain the latest documents and/or specifications,

and before placing any product order.

Copies of documents which have an ordering number and are referenced in this specification, or other Intel

literature, may be obtained from:

Intel Corporation

http://www.intel.com

or, call 1-800-548-4725

* Third-party brands and names are the property of their respective owners.

EHCI Revision 1.0 3/12/2002

USB 2.0

Revision History

Revision Issue Date Comments

0.8a 7/20/1999 Initial Revision

0.8b 8/10/1999 Added information in data structures to support split transactions,

etc. Started adding information into operational model (Chapter 4).

0.9 rc1 12/21/1999 Significant additions to complete definition for register space, data

structures and operational model.

0.9 rc2 1/3/2000 Updated based on 0.9rc1 feedback.

0.9 rc5 1/12/2000 Updated based on 0.9 rc2 feedback. Internal, incremental revisions

account rcX jump.

0.9 1/13/2000 Editorial changes from 0.9 rc5.

0.91 7/6/2000 Update for yellow cover release. Also includes additions for debug

port.

0.95 rc1 9/26/2000 Editorial updates. Deleted Chapter 5, Legacy Keyboard.

0.95 11/10/2000 Final editorial updates.

0.96 rc1 4/23/2001 Editorial clarifications; Fix for erratum on handling CErr during

Interrupt split transactions and new features for managing frame-

wrap FS/LS interrupt, Asynchronous Park-mode, FS/LS

Rebalancing and new EHCI ownership semaphores.

0.96.rc2 5/30/2001 Fixed numerous typos, relaxed requirements on park mode, added

CErr handling for FS/LS Setup transactions and numerous other

clarifications.

0.96.rc3 6/12/2001 Added requirement to handling of full-speed isochronous-IN data

streams (for compatibility).

0.96 6/20/2001 Final editorial edits, pagination, etc.

1.0 rc1 1/31/2002 Editorial changes accumulated from industry feedback.

1.0 3/13/2002 Editorial changes accumulated during Licensee Review Period.

NOTE TO SOFTWARE DEVELOPERS:

Revisions of the EHCI specification have introduced new features in the programming interface. Software

must not attempt to use features defined in recent revisions of the specification on host controllers designed

to older revisions. A summary of new features, per revision is provided below.

Revision Software-visible New Feature

• Frame Span Traversal Nodes (FSTN), see Section 3.7.

• Rebalance Lockout (I-Bit), see Sections 3.6, 4.12.2.5

• Asynchronous Park Mode, see Sections 2.2.4, 2.3.1, and 4.10.3.2.

• EHCI Extended Capabilities, see Section 5.

0.96

• Legacy Support, see Section 5.1

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wwllzz88

2014-03-15

打不开虽然后缀是.pdf 不知为啥
chenhy888tw

2013-01-30

虽然是dos下的代码，但是可以学到如何操作spi总线，为编程提供参考。

点点吃得太多了

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