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### Universal Host Controller Interface (UHCI) 设计指南 #### 概述《Universal Host Controller Interface (UHCI)》设计指南是一份重要的文档，它详细介绍了UHCI标准的技术规范及其在USB主机控制器中的应用。这份文档最初发布于1996年3月，版本号为1.1，并且明确指出文档中的信息处于审阅阶段，可能会有所更改。 #### UHCI的背景与定义 **Universal Host Controller Interface (UHCI)** 是一种用于连接USB设备到计算机系统的接口标准，由Intel公司开发。UHCI的设计目的是为了提供一个统一的接口，使得USB主机控制器能够支持各种类型的USB设备，包括低速、全速和高速设备。通过实现UHCI标准，硬件制造商可以创建兼容多种USB设备的主机控制器，从而简化了USB设备的集成过程。 #### 主要特性与功能 - **兼容性**: UHCI旨在确保向后兼容性，支持所有类型的USB设备。 - **灵活性**: 该接口提供了灵活的配置选项，允许根据具体的应用需求进行调整。 - **性能**: 通过优化数据传输路径和降低延迟，UHCI提高了USB设备的整体性能。 - **易用性**: 设计简单直观，便于开发者快速上手。 #### 技术细节 UHCI技术的核心在于其独特的架构设计，主要包括以下几个方面： 1. **控制器接口**: 定义了主机控制器与操作系统之间的通信协议，确保了数据传输的一致性和可靠性。 2. **设备管理**: 提供了一套完整的机制来管理连接的USB设备，包括设备枚举、配置设置以及错误处理等。 3. **数据传输**: 规定了高效的数据传输方式，如批量传输、中断传输等，以满足不同应用场景的需求。 4. **电源管理**: 实现了对USB设备的电源控制功能，可以在不使用时自动进入低功耗模式，节省能源。 5. **错误检测与恢复**: 强化了系统的稳定性和健壮性，能够在出现故障时及时发现并恢复系统正常运行。 #### 许可协议 UHCI设计指南还特别强调了许可协议的重要性。文档中明确指出，任何想要实施UHCI标准的个人或组织都必须遵守相应的许可条款。这些条款通常涉及专利使用权、版权归属等问题，并规定了使用该技术的条件和限制。例如，采用UHCI标准的产品必须是USB规范的遵循者，并且签署了一份名为“USB Reciprocal Covenant”的协议。 #### 结论《Universal Host Controller Interface (UHCI)》设计指南不仅为USB主机控制器的设计提供了详尽的技术指导，还强调了遵守相应许可协议的重要性。通过理解和应用UHCI标准，硬件制造商可以开发出更加高效、兼容性更强的USB主机控制器产品，从而推动整个USB生态系统的发展。随着技术的进步和市场需求的变化，UHCI标准也在不断地演进和完善之中，以适应更广泛的应用场景。

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Universal Host Controller Interface (UHCI)

Design Guide

REVISION 1.1

March 1996

The information in this document is under review and is subject to change.

Universal Host Controller Interface (UHCI), Revision 1.1

iii iii

Universal Host Controller Agreement

This is a royalty-free, reciprocal license for Adopters of the USB Specification who wish to implement the Universal Host

Controller interface designed by Intel, and described in the Universal Host Controller Interface (UHCI) Design Guide, in their

USB-compliant products. By implementing this specification, you (“User”) are agreeing to be bound by the terms of this

agreement. If you do not agree to them, then you have no license to use the specification, and you should destroy these materials or

return them to Intel.

Eligible Licensees: The licenses granted in this Agreement shall only extend to a party who has executed and is bound by the

agreement executed by Intel and other parties entitled “USB Reciprocal Covenant” relating to the USB Specification.

Agreement: Effective as of User’s acceptance of this Agreement, and subject to its terms and conditions, Intel Corporation (“Intel”) and

User agree as follows:

License: Intel and User each grant to the other and its parents and subsidiaries, under any claim of a patent or patent application

otherwise infringed, a non-exclusive, royalty-free, non-transferable, world-wide license, without rights to sublicense, to make or have

made such party’s products which implement the Interface solely in connection with implementing the USB Specification, and to use,

sell, offer to sell, and import such products, where infringement of such claims would not have occurred but for the implementation and

incorporation of the Interface in such products, and there is no feasible alternative to such infringement.

“Interface” means interface specification described in the document entitled “Universal Host Controller Interface (UHCI) Design Guide”

published by Intel, and any circuitry described therein.

“USB Specification” means a revision of the “Universal Serial Bus Specification,” numbered 1.0 or greater, published and made

available for industry licensing by Intel and the other USB promoters.

No Other Licenses. Except for the rights expressly provided by this Agreement, neither party grants or receives, by implication, or

estoppel, or otherwise, any rights under any patents or other intellectual property rights. Licenses to the USB Specification are to be

granted by a separate document.

LIMITATION OF LIABILITY: The Interface is provided "AS IS" without warranty of any kind. INTEL OFFERS NO OTHER WARRANTY

EITHER EXPRESS OR IMPLIED INCLUDING THOSE OF MERCHANTABILITY, NONINFRINGEMENT OF THIRD-PARTY

INTELLECTUAL PROPERTY OR FITNESS FOR A PARTICULAR PURPOSE. NEITHER INTEL NOR ITS SUPPLIERS SHALL BE

LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,

BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER LOSS) ARISING OUT OF THE USE OF OR INABILITY

TO USE THE INTERFACE, EVEN IF INTEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME

JURISDICTIONS PROHIBIT THE EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,

THE ABOVE LIMITATION MAY NOT APPLY TO YOU.

TERMINATION OF THIS LICENSE: Intel may terminate this license at any time if you are in breach of any of its terms and conditions.

Upon termination, you will immediately destroy the Interface or return all copies of the Interface to Intel along with any copies you have

made.

U.S. GOVERNMENT RESTRICTED RIGHTS: The Interface is provided with "RESTRICTED RIGHTS." Use, duplication or disclosure by

the Government is subject to restrictions set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor. Use of the

Interface by the Government constitutes acknowledgment of Intel's rights in them .

APPLICABLE LAWS: Any claim arising under or relating to this Agreement shall be governed by the laws of Delaware. You may not

export the Interface in violation of applicable export laws.

Universal Host Controller Interface (UHCI), Revision 1.1

v v

Table Of Contents

1. OVERVIEW.........................................................................................................................................2

1.1 DATA TRANSFER TYPES ................................................................................................................3

1.1.1 FRAME TIME FOR DATA TRANSFERS..................................................................................................... 4

1.2 UHCI DATA STRUCTURES ..............................................................................................................5

1.2.1 FRAME LIST.............................................................................................................................................. 5

1.2.2 TRANSFER DESCRIPTORS...................................................................................................................... 5

1.2.3 QUEUE HEADS......................................................................................................................................... 6

1.3 SCHEDULING...................................................................................................................................7

1.3.1 HARDWARE CONTROL FOR FULL SPEED TRANSFER BANDWIDTH RECLAMATION........................... 7

1.4 ROOT HUB/PORTS ..........................................................................................................................7

2. REGISTER DESCRIPTION...............................................................................................................10

2.1 USB I/O REGISTERS...................................................................................................................... 11

2.1.1 USBCMDUSB COMMAND REGISTER..................................................................................................11

2.1.2 USBSTS

USB STATUS REGISTER........................................................................................................13

2.1.3 USBINTR

USB INTERRUPT ENABLE REGISTER..................................................................................14

2.1.4 FRNUM

FRAME NUMBER REGISTER...................................................................................................14

2.1.5 FLBASEADD

FRAME LIST BASE ADDRESS REGISTER.......................................................................15

2.1.6 START OF FRAME (SOF) MODIFY REGISTER .......................................................................................15

2.1.7 PORTSC

PORT STATUS AND CONTROL REGISTER...........................................................................16

2.2 PCI CONFIGURATION REGISTERS (USB).................................................................................... 19

2.2.1 CLASSCCLASS CODE REGISTER .......................................................................................................19

2.2.2 USBBASE

IO SPACE BASE ADDRESS REGISTER ..............................................................................19

2.2.3 SBRN

SERIAL BUS RELEASE NUMBER REGISTER.............................................................................19

3. DATA STRUCTURES .......................................................................................................................20

3.1 FRAME LIST POINTER...................................................................................................................20

3.1.1 FRAME LIST POINTER (DWORD)...........................................................................................................20

3.2 TRANSFER DESCRIPTOR (TD) .....................................................................................................20

3.2.1 TD LINK POINTER (DWORD 0: 00-03H)...................................................................................................21

3.2.2 TD CONTROL AND STATUS (DWORD 1: 04-07

H) ...................................................................................22

3.2.3 TD TOKEN (DWORD 2: 08-0B

H)...............................................................................................................24

3.2.4 TD BUFFER POINTER (DWORD 3: 0C-0F

H) ............................................................................................25

3.2.5 RESERVED FOR SOFTWARE (DWORDS [7:4]).......................................................................................25

3.3 QUEUE HEAD (QH) ........................................................................................................................ 25

3.3.1 QUEUE HEAD LINK POINTER (DWORD 0: 00-03H).................................................................................25

3.3.2 QUEUE ELEMENT LINK POINTER (DWORD 1: 04-07

H) ..........................................................................26

3.4 SCRIPT AND DATA TRANSFER PRIMITIVES................................................................................26

3.4.1 EXECUTING THE SCHEDULE .................................................................................................................26

3.4.2 TRANSFER QUEUING .............................................................................................................................31

4. INTERRUPTS ...................................................................................................................................35

4.1 TRANSACTION BASED.................................................................................................................. 35

4.1.1 CRC ERROR / TIME-OUT ........................................................................................................................35

4.1.2 INTERRUPT ON COMPLETION (IOC)......................................................................................................35

4.1.3 SHORT PACKET DETECT (SPD) .............................................................................................................36

4.1.4 SERIAL BUS BABBLE ..............................................................................................................................36

4.1.5 STALLED..................................................................................................................................................36

4.1.6 DATA BUFFER ERROR............................................................................................................................36

4.1.7 BIT STUFF ERROR ..................................................................................................................................36

剩余46页未读，继续阅读

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yingzimi

2018-06-03

内容是1.1的，比较经典

Universal Host Controller Interface (UHCI)

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