PCI Express Base Specification, Rev. 4.0 Version 1.0
PCI Express
®
Base Specification
Revision 4.0 Version 1.0
September 27, 2017
PCI Express Base Specification, Rev. 4.0 Version 1.0
2
Revision Revision History Date
1.0
Initial release.
07/22/2002
1.0a
Incorporated Errata C1-C66 and E1-E4.17.
04/15/2003
1.1
Incorporated approved Errata and ECNs.
03/28/2005
2.0
Added 5.0 GT/s data rate and incorporated approved Errata and ECNs.
12/20/2006
2.1 Incorporated Errata for the PCI Express Base Specification, Rev. 2.0
(February 27, 2009), and added the following ECNs:
• Internal Error Reporting ECN (April 24, 2008)
• Multicast ECN (December 14, 2007, approved by PWG May 8, 2008)
• Atomic Operations ECN (January 15, 2008, approved by PWG April 17, 2008)
• Resizable BAR Capability ECN (January 22, 2008, updated and approved by
PWG April 24, 2008)
• Dynamic Power Allocation ECN (May 24, 2008)
• ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008)
• Latency Tolerance Reporting ECN (22 January 2008, updated 14 August 2008)
• Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last updated
June 4, 2007)
• Extended Tag Enable Default ECN (September 5, 2008)
• TLP Processing Hints ECN (September 11, 2008)
•
TLP Prefix ECN (December 15, 2008)
03/04/2009
3.0
Added 8.0 GT/s data rate, latest approved Errata, and the following ECNs:
• Optimized Buffer Flush/Fill ECN (8 February 2008, updated 30 April 2009)
• ASPM Optionality ECN (June 19, 2009, approved by the PWG August 20, 2009)
• Incorporated End-End TLP Changes for RCs ECN (26 May 2010) and Protocol
Multiplexing ECN (17 June 2010)
11/10/2010
3.1 Incorporated feedback from Member Review
Incorporated Errata for the PCI Express® Base Specification Revision 3.0
Incorporated M-PCIe Errata (3p1_active_errata_list_mpcie_28Aug2014.doc and
3p1_active_errata_list_mpcie_part2_11Sept2014.doc)
Incorporated the following ECNs:
• ECN: Downstream Port containment (DPC)
• ECN: Separate Refclk Independent SSC (SRIS) Architecture
• ECN: Process Address Space ID (PASID)
• ECN: Lightweight Notification (LN) Protocol
• ECN: Precision Time Measurement
• ECN: Enhanced DPC (eDPC)
• ECN: 8.0 GT/s Receiver Impedance
• ECN: L1 PM Substates with CLKREQ
• ECN: Change Root Complex Event Collector Class Code
• ECN: M-PCIe
• ECN: Readiness Notifications (RN)
• ECN: Separate Refclk Independent SSC Architecture (SRIS) JTOL and SSC
Profile Requirements
10/8/2014
3.1a Minor update:
Corrected: Equation 4.3.9 in Section 4.3.8.5., Separate Refclk With Independent SSC
(SRIS) Architecture. Added missing square (exponent=2) in the definition of B.
B = 2.2 × 10^12 × (2.π)^2 where ^= exponent.
12/5/2015
4.0 Version 0.3: Based on PCI Express® Base Specification Revision 3.1
(October 8, 2014) with some editorial feedback received in December 2013.
• Added Chapter 9, Electrical Sub-block: Added Chapter 9 (Rev0.3-11-30-
13_final.docx)
• Changes related to Revision 0.3 release
• Incorporated PCIe-relevant material from PCI Bus Power Management Interface
Specification (Revision 1.2, dated March 3, 2004). This initial integration of the
material will be updated as necessary and will supercede the standalone Power
Management Interface specification.
Version 0.5 (12/22/14, minor revisions on 1/26/15, minor corrections 2/6/15)
• Added front matter with notes on expected discussions and changes.
• Added ECN:Retimer (dated October 6, 2014)
• Corrected Chapter 4 title to, “Physical Layer Logical Block”.
• Added Encoding subteam feedback on Chapter 4
• Added Electrical work group changes from PCIe Electrical Specification Rev 0.5
RC1 into Chapter 9
Version 0.7: Based on PCI Express® Base Specification Version 4.0 Revision 0.5
(11/23/2015)
• Added ECN_DVSEC-2015-08-04
2/6/2015
11/24/2015
PCI Express Base Specification, Rev. 4.0 Version 1.0
3
Revision Revision History Date
• Applied ECN PASID-ATS dated 2011-03-31
• Applied PCIE Base Spec Errata: PCIe_Base_r3 1_Errata_2015-09-18
except:
o B216; RCIE
o B256; grammar is not clear
• Changes to Chapter 7. Software Initialization and Configuration per
PCIe_4.0_regs_0-3F_gord_7.docx
• Added Chapter SR-IOV Spec Rev 1.2
(Rev 1.1 dated September 8, 2009 plus:
o SR-IOV_11_errata_table.doc
o DVSEC
o 3.1 Base Spec errata)
• Added Chapter ATS Spec Rev 1.2
(Rev 1.1 dated January 26, 2009 plus:
o ECN-PASID-ATS
o 3.1 Base Spec errata)
2/18/2016 Changes from the Protocol Working Group
• Applied changes from the following documents:
o FC Init/Revision | scaled-flow-control-pcie-base40-2016-01-
07.pdf (Steve.G)
o Register updates for integrated legacy specs | PCIe_4.0_regs_0-
3F_gord_8.docx (GordC)
o Tag Scaling PCIe 4_0 Tag Field scaling 2015-11-23 clean.docx
(JoeC)
o MSI/MSI-X | PCIe 4_0 MSI & MSI-X 2015-12-18 clean.docx
(JoeC); register diagrams TBD on next draft.
o REPLAY_TIMER/Ack/FC Limits | Ack_FC_Replay_Timers_ver8
(PeterJ)
Chapter 10. SR-IOV related changes:
• Incorporated “SR-IOV and Sharing Specification” Revision 1.1 dated
January 20, 2010 (sr-iov1_1_20Jan10.pdf) as Chapter 10, with changes
from the following documents
o Errata for the PCI Express® Base Specification Revision 3.1,
Single Root I/O Virtualization and Sharing Revision 1.1, Address
Translation and Sharing Revision 1.1, and M.2 Specification
Revision 1.0: PCIe_Base_r3 1_Errata_2015-09-18_clean.pdf
o ECN__Integrated_Endpoints_and_IOV_updates__19 Nov
2015_Final.pdf
o Changes marked “editorial” only in marked PDF: sr-
iov1_1_20Jan10-steve-manning-comments.pdf
Chapter 9. Electrical Sub-Block related changes:
o Source: WG approved word document from Dan Froelich
(FileName: Electrical-
PCI_Express_Base_4.0r0.7_April_7_wg_approved_redo_for_figure_corrupt
ion.docx.)
2/18/16
4/26/16 [snapshot]
5/23/16[snapshot]
4.0 Version 0.7 continued…
Chapter 4. PHY Logical Changes based on:
• Chapter4-PCI_Express_Base_4 0r0 7_May3_2016_draft.docx
Chapter 7. . PHY Logical Changes based on:
• PCI_Express_Base_4 0r0 7_Phy-Logical_Ch7_Delta_28_Apr_2016.docx
- - - - - - - - - Changes incorporated into the August 2016 4.0 r0.7 Draft PDF - -- - - - - - - - - -
June 16 Feedback from PWG on the May 2016 snapshot
PWG Feedback on 4.0 r0.7 Feb-Apr-May-2016 Drafts
*EWG Feedback:
---CB-PCI_Express_Base_4.0r0.7_May-2016 (Final).fdf
---EWG f/b: Electrical-
PCI_Express_Base_4.0r0.7_April_7_wg_approved_redo_for_figure_corruption_Broadco.d
ocx
*PWG Feedback:
-PWG 0.7 fix list part1 and part 2.docx
-PWG 0 7 fix list part3a.docx
8/30/16
PCI Express Base Specification, Rev. 4.0 Version 1.0
4
Revision Revision History Date
---PCI_Express_Base_4.0r0.7_pref_April-2016_chp5_PM_stuff_only_ver3.docx
---PCI_Express_Base_4.0r0.7_pref_April-2016_chp5_PM_stuff_only_ver3.docx
---scaled-flow-control-pcie-base40-2016-07-07.pdf
---ECN_NOP_DLLP-2014-06-11_clean.pdf
---ECN_RN_29_Aug_2013.pdf
---3p1_active_errata_list_mpcie_28Aug2014.doc
---3p1_active_errata_list_mpcie_part2_11Sept2014.doc
---lane-margining-capability-snapshot-2016-06-16.pdf
---Emergency Power Reduction Mechanism with PWRBRK Signal ECN
-PWG 0 7 fix list part4.docx
---ECN_Conventional_Adv_Caps_27Jul06.pdf
---10-bit Tag related SR-IOV Updates
*Other:
---Merged Acknowledgements back pages from SR-IOV and ATS specifications into the
main base spec. Acknowledgements page.
- - - - - - - - - Changes since August 2016 for the September 2016 4.0 r0.7 Draft PDF- - - - -
Applied:
PWG Feedback/Corrections on August draft
ECN_SR-IOV_Table_Updates_16-June-2016.doc
- - - - - - - Changes since September 28 2016 for the October 2016 4.0 r0.7 Draft PDF- - - -
EWG:
Updates to Chapter 9- Electrical Sub-block (Sections: 9.4.1.4, 9.6.5.1, 9.6.5.2, 9.6.7)
PWG:
Updates to Sections: 3.2.1, 3.3, 3.5.1, 7.13, 7.13.3 (Figure: Data Link Status Register)
- - - - - - - Changes to the October 13 2016 4.0 r0.7 Draft PDF- - - -
EWG:
Updates to Chapter 9- Electrical Sub-block (Section 9.3.3.9 and Figure 9-9 caption)
- - - - - - - Changes to the November 3 2016 4.0 r0.7 Draft PDF- - - -
Section 2.6.1 Flow Control Rules: Updated Scaled Flow Control sub-bullet under FC
initialization bullet (before Table 2-43)
- - - - - - - Changes to the November 11 2016 4.0 r0.7 Draft PDF- - - -
Added M-PCIe statement to the Open Issues page
Updated date to November 11, 2016
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Version 0.9: Based on PCI Express® Base Specification Version 4.0
Revision 0.7 (11/11/2016)
Incorporated the following ECNs:
---ECN-Hierarchy_ID-2017-02-23
---ECN_FPB_9_Feb_2017
---ECN Expanded Resizable BARs 2016-04-18
---ECN-VF-Resizable-BARs_6-July-2016
--- Chapter 7 reorganized:
• New section 7.6 created per a PWG-approved reorganization to move sections
7.5, 7.6,. and 7.10 to subsections 7.6.1 through 7.6.3 resp.
• New section 7.7 created per a PWG-approved reorganization to move sections
7.7, 7.8,.7.12, 7.13, 7.40, 7.41 and 7.20 to subsections 7.7.1 through 7.7.7
resp.
• New section 7.9 created per a PWG-approved reorganization to move sections
7.15, 7.22, 7.16, 7.23, 7.39, 7.24, 7.17, 7.18, 7.21, 7.25, 7.28, 7.30, 7.33, 7.34,
7.35, 7.38, and 7.42 to subsections 7.9.1 through 7.9.17 resp.
---Removed Chapter 8: M-PCIe Logical Sub-Block
---Updated Chapter 9 (8 now), EWG Updates to Chapter 9- Electrical Sub-block per:
Chapter9-PCI_Express_Base_4 0r09_March_30--2017_approved.docx
---Updated Chapter 4: Physical Layer Logical Block per
PCI_Express_Base_4 0_r0 9_Chapter4_Final_Draft.docx
---Updated Figures in Chapter 10: ATS Specification
9/28/16
10/7/16
10/21/16
11/3/16
11/11/16
April 28 2017
PCI Express Base Specification, Rev. 4.0 Version 1.0
5
Revision Revision History Date
---Removed Appendix H: M-PCIe timing Diagrams
---Removed Appendix I: M-PCIe Compliance Patterns, pursuant to removing the M-PCIe
Chapter this 0.9 version of the 4.0 Base Spec.
---Added Appendix H: Flow Control Update Latency and ACK Update Latency Calculations
---Added Appendix I: Vital Product Data (VPD)
---Updated editorial feedback on the Appendix section per:
PCI_Express_Base_4.0r0.7_appendixes_November-11-2016_combined-editorial.docx
---Deleted references to M-PCIe throughout the document.
---Updated Chapter 9 (8 now), EWG Updates to Chapter 9- Electrical Sub-block per:
Chapter9-PCI_Express_Base_4 0r09_March_30--2017_approved.docx
---Updated Chapter 4: Physical Layer Logical Block per
PCI_Express_Base_4 0_r0 9_Chapter4_Final_Draft.docx
---Updated Figures in Chapter 10: ATS Specification
---Added Appendix H: Flow Control Update Latency and ACK Update Latency Calculations
---Following items that were marked deleted in the Change Bar version of the April 28
th
snapshot have been “accepted” to no longer show up:
pp 1070: Lane Equalization Control 2 Register (Offset TBD) Comment: Deleted per: PCI_Express_Base_4 0r0
7_Phy-Logical_Ch7_Delta_28_Apr_2016.docx
pp 1074: Physical Layer 16.0 GT/s Margining Extended Capability section
Comment: Deleted per: PCI_Express_Base_4 0r0 7_Phy-Logical_Ch7_Delta_28_Apr_2016.docx
Comment: Replaced by Section, “Lane Margining at the Receiver Extended Capability” per Fix3a #83 lane-margining-
capability-snapshot-2016-06-16.pdf
---Incorporated: PCIe 4_0 Tag Field scaling 2017-03-31.docx
---Vital Product Data (VPD)
-----Added Section 6.28
-----Added Section 7.9.4
---Incorporated feedback from April 28
th
snapshot.[source: 3 fdf files]
---Completed editorial feedback on the Appendix section per:
PCI_Express_Base_4.0r0.7_appendixes_November-11-2016_combined-editorial.docx
---Incorporated ECN EMD for MSI 2016-05-10
---Updated per: PWG F2F changes from: PCI_Express_Base_4.0r0.7_pref_November-11-
2016-F2F-2017-03-16-2017-03-30-sdg.docx
---Updated figures per following lists (Gord Caruk):
PCIe_4 0_fix_drawing_items.doc
PCIe_4 0_fix_drawing_items_part2.doc
May 26, 2017
Version 0.91
***Note this version will be used as the base for the PCI Express® Base Specification
Revision 5.0***
Item numbers are with reference to PWG CheckList (https://members.pcisig.com/wg/PCIe-
Protocol/document/10642)
---Moved Flattening Portal Bridge Section 7.10 to Section 7.8.10. PWG Checklist Items
#12.1
---Fixed misc. feedback that needed clarification from the 0.9 version.
Issues fall under the categories of figure updates, broken cross references.
Also incorporated feedback received from member review of the 4.0 version rev. 0.9
Base Spec.
---Updated to reconcile issues related to incorporating the Extended Message Data for MSI
ECN. PWG Checklist Items #22
---Completed incorporating all resolved editorial items from PWG Checklist Items #14,
14.1,15.1, 36, 42.
TBD: Some minor editorial items from #13, #14 and #15 have been deferred to post
0.91 by reviewers.
TBD: Errata and NPEM ECN
August 17, 2017
- 1
- 2
前往页