sdram controller sdram控制器

<?xml version="1.0" encoding="UTF-8"?> <Component Name="zma_sdr16" Text="zachary sdram16" Type="Memory" Ver="1.0" Custom="true" DRCError="false" Access="RW" Help=""> <MasterSlavePorts> <SlavePort Name="wb ports" Prefix="wb" ADR="S_ADR_I" DAT1="S_DAT_I" WE="S_WE_I" SEL="S_SEL_I" STB="S_STB_I" CYC="S_CYC_I" LOCK="S_LOCK_I" CTI="S_CTI_I" BTE="S_BTE_I" DAT2="S_DAT_O" ACK="S_ACK_O" ERR="S_ERR_O" RTY="S_RTY_O"/> </MasterSlavePorts> <ClockPort Name="CLK_I" UPort="CLK_I"/> <ResetPort Name="RST_I" UPort="RST_I"/> <ExternalPorts> <ExternalPort Name="sdr_CLK" Width="1" Type="output" UPort="sdr_CLK" /> <ExternalPort Name="sdr_CKE" Width="1" Type="output" UPort="sdr_CKE" /> <ExternalPort Name="sdr_CSn" Width="1" Type="output" UPort="sdr_CSn" /> <ExternalPort Name="sdr_RASn" Width="1" Type="output" UPort="sdr_RASn" /> <ExternalPort Name="sdr_CASn" Width="1" Type="output" UPort="sdr_CASn" /> <ExternalPort Name="sdr_WEn" Width="1" Type="output" UPort="sdr_WEn" /> <ExternalPort Name="sdr_BA" Width="2" Type="output" UPort="sdr_BA" /> <ExternalPort Name="sdr_A" Width="12" Type="output" UPort="sdr_A" /> <ExternalPort Name="sdr_DQM" Width="2" Type="output" UPort="sdr_DQM" /> <ExternalPort Name="sdr_DQ" Width="16" Type="inout" UPort="sdr_DQ" /> </ExternalPorts> <Files> <TopFile Name="zma_sdr16_top"/> <File Name="../components/zma_sdr16/rtl/verilog/zma_sdr16.v"/> <File Name="../components/zma_sdr16/rtl/verilog/zma_sdr16_v2.v"/> <File Name="../components/zma_sdr16/rtl/verilog/pmi_pll.v"/> <File Name="../components/zma_sdr16/rtl/verilog/wb32_wb16.v"/> <File Name="../components/zma_sdr16/rtl/verilog/zma_sdr16_top.v"/> </Files> <DeviceDriver InitRoutine="" StructName=""> <DDstruct> <DDSElem MemberName="lookupReg" MemberType = "DeviceReg_t" Type="uninitialized" Value=""/> </DDstruct> <Software> </Software> </DeviceDriver> <Parms> <Parm Name="InstanceName" Type="string" Value="sdr16" Text="Instance Name" isiname="true"/> <Parm Name="BASE_ADDRESS" Type="Integer" Value="0x02000000" Text="Base Address" isba="true"/> <Parm Name="SIZE" Type="Integer" Value="1048576" Text="Address Width" issize="true" Enable="true"/> <Parm Name="ADDRESS_LOCK" Type="Define" Value="undef" Text="Lock Address"/> <Parm Name="DISABLE" Type="Define" Value="undef" Text="Disable" isuse="true"/> <Parm Name="REGGED_SDR_DI" Text="sdram read data regestered" Type="Define" Value="def" CompilerFlag="aaaa"/> <Parm Name="COL_BITS" Text="column width" Type="List" Value="8" ListValues="8" isparm="true"/> <Parm Name="ROW_BITS" Text="row width" Type="List" Value="12" ListValues="10,11,12" isparm="true"/> <Parm Name="BA_BITS" Text="bank width" Type="List" Value="2" ListValues="1,2" isparm="true"/> <Parm Name="SYS_FREQ" Text="SYS_FREQ" Type="Frequency" Value="50" isparm="true"/> </Parms> <GUIS Columns="2"> <GUI Widget="Text" Span="1" Name="InstanceName"/> <GUI Widget="Text" Span="1" Name="BASE_ADDRESS"/> <GUI Widget="Text" Span="1" Name="SIZE"/> <GUI Widget="Check" Span="2" Name="REGGED_SDR_DI"/> <GUI Widget="Combo" Span="1" Name="COL_BITS"/> <GUI Widget="Combo" Span="1" Name="ROW_BITS"/> <GUI Widget="Combo" Span="1" Name="BA_BITS"/> </GUIS> </Component>