CRC电路实现详解与实现
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38
CIRCUIT CELLAR
®
•
www.circuitcellar.com
January 2010 – Issue 234
igure 1
—This is a USB CRC5 implementation as LFSR using generator polynomial
G(x) = x
5
+ x
2
+ 1.
Data
Figure 2—
This is a parallel CRC block. The next state CRC output is
a function of the current state CRC and the data.
M-bit CRC
Next state
M-bit CRC
Output
Parallel
CRC
Generator
M-bit Data
input
Do you understand the mechanics of the cyclic redundancy check (CRC) well
enough to build a customized parallel CRC circuit described by an arbitrary
CRC generator polynomial? This article covers a practical method of generating
Verilog or VHDL code for the parallel CRC. The result is the fast generation of
a parallel CRC code for an arbitrary polynomial and data width.
A Practical Parallel CRC
Generation Method
M
F
EATURE
A
RTICLE
by Evgeni Stavinov
ost electrical and computer
engineers are familiar with the
cyclic redundancy check (CRC). Many
know that it’s used in communication
protocols to detect bit errors, and that it’s
essentially a remainder of the modulo-2
long division operation. Some have had
closer encounters with the CRC and
know that it’s implemented as a linear
feedback shift register (LFSR) using flip-flops and XOR
gates. They likely used an online tool or an existing
example to generate parallel CRC code for a design. But
very few engineers understand the mechanics of the
CRC well enough to build a customized parallel CRC
circuit described by an arbitrary CRC generator polyno-
mial. What about you?
In this article, I’ll present a practical method for gen-
erating Verilog or VHDL code for the parallel CRC. This
method allows for the fast generation of a parallel CRC
code for an arbitrary polynomial and data width. I’ll also
briefly describe other interesting methods and provide
more information on the subject.
So why am I covering parallel CRC? There are several
existing tools that can generate the code, and a lot of
examples for popular CRC polynomials. However, it’s
often beneficial to understand the underlying principles
in order to implement a customized circuit or make
optimizations to an existing one. This is a subject every
practicing logic design engineer should understand.
CRC OVERVIEW
Every modern communication protocol uses one or
more error-detection algorithms. CRC is by far the most
popular. CRC properties are defined by the generator poly-
nomial length and coefficients. The protocol specification
usually defines CRC in hex or polynomial notation. For
Figure 1
—This is a USB CRC5 implementation as LFSR using generator polynomial
G(x) = x
5
+ x
2
+ 1.
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