Uart RS232 Verilog FGPA实现 带testbench，实现了串口数据接受口接收一个字节数据后将这一个字节通过输出发送出去，更详细的看读写模块
顶级模块如下：
module UartRs232(clk50M, resetKey, uTx, uRx);
`include "infoDefine.v"
input clk50M;
input resetKey;
input uRx; //接受数据
output uTx; //发送数据
wire uTx;
wire [7:0]readNum;
wire readOkClk, writeOkClk;
reg [15:0]clkCount; //最小细分频计数器
reg minUartClk; //细分频时钟
//实时读取数据
UartRead myUartRead(.minUartClk(minUartClk), .resetKey(resetKey),
.uRx(uRx), .readNum(readNum), .readOkClk(readOkClk));
//将读到的数据从发送口发出去
UartWrite myUartWrite(.minUartClk(minUartClk), .resetKey(resetKey),
.writeStart(readOkClk), .uTx(uTx), .writeNum(readNum), .writeOkClk(writeOkClk));
//产生对应波特率时钟
always @(posedge clk50M or negedge resetKey)
begin
if (~resetKey)
begin
clkCount <= 16'd0;
minUartClk <= 1'b0;
end
else if (clkCount >= `UCLK_COUNT-1'b1)
begin
clkCount <= 16'd0;
minUartClk <= 1'b1;
end
else
begin
clkCount <= clkCount + 1'b1;
minUartClk <= 1'b0;
end
end
endmodule
