AT89C55的介绍资源-CSDN文库

89C55

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PDIP

(T2) P1.0

(T2 EX) P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

(WR) P3.6

(RD) P3.7

XTAL2

XTAL1

GND

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

P2.4 (A12)

P2.3 (A11)

P2.2 (A10)

P2.1 (A9)

P2.0 (A8)

Features

• Compatible with MCS-51

™

Products

• 20K Bytes of In-System Reprogrammable Flash Memory

– Endurance: 1,000 Write/Erase Cycles

• Fully Static Operation: 0 Hz to 33 MHz

• Three-level Program Memory Lock

• 256 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Three 16-bit Timer/Counters

• Eight Interrupt Sources

• Low-power Idle and Power-down Modes

Description

The AT89C55 is a low-power, high-performance CMOS 8-bit microcomputer with 20K

bytes of Flash programmable and erasable read only memory. The device is manu-

factured using Atmel’s high-density nonvolatile memory technology and is compatible

with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows

the program memory to be reprogrammed in-system or by a conventional nonvolatile

memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic

chip, the Atmel AT89C55 is a powerful microcomputer which provides a highly-flexible

and cost-effective solution to many embedded control applications.

Rev. 0580E–02/00

8-bit

Microcontroller

with 20K Bytes

Flash

AT89C55

Pin Configurations

PQFP/TQFP

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

PO.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

(WR)P3.6

(RD) P3.7

XTAL2

XTAL1

GND

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

PLCC

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

PO.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

(WR)P3.6

(RD) P3.7

XTAL2

XTAL1

GND

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

AT89C55

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bi-directional I/O port. As an

output port, each pin can sink eight TTL inputs. When 1s

are written to port 0 pins, the pins can be used as high-

impedance inputs.

Port 0 can also be configured to be the multiplexed low-

order address/data bus during accesses to external pro-

gram and data memory. In this mode, P0 has internal

pullups.

Port 0 also receives the code bytes during Flash program-

ming and outputs the code bytes during program

verification. External pullups are required during program

verification.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pullups.

The Port 1 output buffers can sink/source four TTL inputs.

When 1s are written to Port 1 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally being pulled low will source

current (I

) because of the internal pullups.

In addition, P1.0 and P1.1 can be configured to be the

timer/counter 2 external count input (P1.0/T2) and the

timer/counter 2 trigger input (P1.1/T2EX), respectively, as

shown in the following table.

Port 1 also receives the low-order address bytes during

Flash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pullups.

The Port 2 output buffers can sink/source four TTL inputs.

When 1s are written to Port 2 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 2 pins that are externally being pulled low will source

current (I

) because of the internal pullups.

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX @

DPTR). In this application, Port 2 uses strong internal pul-

lups when emitting 1s. During accesses to external data

memory that use 8-bit addresses (MOVX @ RI), Port 2

emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some

control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pullups.

The Port 3 output buffers can sink/source four TTL inputs.

When 1s are written to Port 3 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 3 pins that are externally being pulled low will source

current (I

) because of the pullups.

Port 3 also serves the functions of various special features

of the AT89C55, as shown in the following table.

Port 3 also receives the highest-order address bit and

some control signals for Flash programming and

verification.

RST

Reset inp1ut. A high on this pin for two machine cycles

while the oscillator is running resets the device.

ALE/PROG

Address Latch Enable is an output pulse for latching the

low byte of the address during accesses to external mem-

ory. This pin is also the program pulse input (PROG

) during

Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6

the oscillator frequency and may be used for external tim-

ing or clocking purposes. Note, however, that one ALE

pulse is skipped during each access to external data

memory.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2),

clock-out

P1.1 T2EX (Timer/Counter 2 capture/reload trigger

and direction control)

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0

(external interrupt 0)

P3.3 INT1

(external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR

(external data memory write strobe)

P3.7 RD

(external data memory read strobe)

AT89C55

Special Function Registers

A map of the on-chip memory area called the Special Func-

tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc-

cupied addresses may not be implemented on the chip.

Read accesses to these addresses will in general return

random data, and write accesses will have an indetermi-

nate effect.

User software should not write 1s to these unlisted loca-

tions, since they may be used in future products to invoke

new features. In that case, the reset or inactive values of

the new bits will always be 0.

Timer 2 Registers Control and status bits are contained in

registers T2CON (shown in Table 2) and T2MOD (shown in

Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L)

are the Capture/Reload registers for Timer 2 in 16-bit cap-

ture mode or 16-bit auto-reload mode.

Interrupt Registers The individual interrupt enable bits are

in the IE register. Two priorities can be set for each of the

six interrupt sources in the IP register.

Data Memory

The AT89C55 implements 256 bytes of on-chip RAM. The

upper 128 bytes occupy a parallel address space to the

Special Function Registers. That means the upper 128

bytes have the same addresses as the SFR space but are

physically separate from SFR space.

When an instruction accesses an internal location above

address 7FH, the address mode used in the instruction

specifies whether the CPU accesses the upper 128 bytes

of RAM or the SFR space. Instructions that use direct

addressing access SFR space.

For example, the following direct addressing instruction

accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper

128 bytes of RAM. For example, the following indirect

addressing instruction, where R0 contains 0A0H, accesses

the data byte at address 0A0H, rather than P2 (whose

address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect

addressing, so the upper 128 bytes of data RAM are avail-

able as stack space.

Table 2. T2CON—Timer/Counter 2 Control Register

T2CON Address = 0C8H Reset Value = 0000 0000B

Bit Addressable

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2

CP/RL2

Bit 7 6543210

Symbol Function

TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK

= 1 or TCLK = 1.

EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.

When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must

be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port

Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial

port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if

Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.

C/T2

Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge

triggered).

CP/RL2

Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 =

0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1.

When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

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